PEX8605, PCI Express Gen 2 Switch, 4 Lanes, 4 Ports The ExpressLane PEX8605 device offers PCI Express switching capability Highlights enabling users to add scalable high bandwidth non-blocking interconnection PEX8605 General Features to a wide variety of applications including control plane applications, o 4-lane, 4-port PCIe Gen2 switch consumer applications and embedded systems. The PEX8605 is well suited Integrate 5.0 GT/s SerDes 2 for fan-out and peer-to-peer applications. o 10 x 10mm , 136-pin aQFN package o Typical Power: 0.8 Watts Low Packet Latency & High Performance The PEX8605 architecture supports packet cut-thru with a maximum latency of PEX8605 Key Features o Standards Compliant 250ns in x1 to x1 configuration. This, combined with low power consumption PCI Express Base Specification, r2.1 and non-blocking internal switch architecture, provides full line rate on all ports (backwards compatible w/ PCIe for low-power applications such as consumer and embedded. The low latency 1.0a/1.1) PCI Power Management Spec, r1.2 enables applications to achieve high throughput and performance. In addition to Microsoft Windows 7 Compliant low latency, the device supports a max payload size of 256 bytes. Dynamic SerDes speed control o High Performance Data Integrity Non-blocking switch fabric Full line rate on all ports The PEX8605 provides end-to-end CRC protection (ECRC) and Poison bit Packet Cut-Thru with 250ns max support to enable designs that require guaranteed error-free packets. PLX also packet latency (x1 to x1) supports data path parity and memory (RAM) error correction as packets pass 256B Max Payload Size through the switch. o Flexible Configuration Ports configurable as x1, x2 Registers configurable with strapping Power Management and Clock Buffering 2 pins, EEPROM, I C, or host software The PEX8605 supports the following power management states: L0, L0s, L1, Reference Clock Buffered Output signals for downstream ports L2/L3 Ready, L2 and L3. Moreover, the PEX8605 supports Vaux along with the Lane and polarity reversal external signal WAKE and the in-band Beacon for the PCIe endpoints to use to Compatible with PCIe 1.0a PM inform the system host to exit the low power savings mode. o Quality of Service (QoS) Eight traffic classes per port The PEX 8605 supports three pairs of PCI Express-compliant, 100MHz, buffered Round-robin source port arbitration HCSL output clocks, one pair for each downstream port of the switch. Each Relaxed PCI Ordering clock output pair can be disabled by software or serial EEPROM when not in o Reliability, Availability, use, for additional power savings. This feature greatly reduces system BOM cost Serviceability by eliminating the need for extra clock buffers on the PCB. visionPAK Per Port Performance Monitoring Per port payload & header counters Interoperability SerDes Eye Capture The PEX8605 is designed to be fully compliant with the PCI Express Base Error Injection and Loopback 2 All ports hot plug capable thru I C Specification r2.1 and is backwards compatible to PCI Express Base (Hot-Plug Controller on every port) Specification r1.1 and r1.0a. Additionally each port supports auto-negotiation and Data Path parity polarity reversal. Furthermore, the PEX8605 is designed for Microsoft Windows Memory (RAM) Error Correction signals 7 compliance. All PLX switches undergo thorough interoperability testing in INTA and FATAL ERR PLXs Interoperability Lab and compliance testing at the PCI-SIG plug-fest to Advanced Error Reporting Port Status bits and GPIO available ensure compatibility with PCI Express devices in the market. Per port error diagnostics JTAG AC/DC boundary scan Device Operation Configuration Flexibility o Power Management The PEX8605 provides several ways to configure its operations. The device can WAKE , Beacon, Vaux support 2 be configured through strapping pins, I C interface, CPU configuration cycles and/or an optional serial EEPROM. This allows for easy debug during the development phase and functional monitoring during the operation phase. PLX Technology, www.plxtech.com Page 1 of 3 8/17/2011, Version 1.1 PEX8605, PCI Express Gen 2 Switch, 4 Lanes, 4 Ports Figure 2 shows a typical fan-out design, where the processor Flexible Port Configurations provides a PCI Express link that needs to be fanned into a larger The PEX8605 flexible architecture supports a number of port number of smaller ports for a variety of I/O functions, each with configurations as required by the target applications as shown in different bandwidth requirements. figure 1 below. Multi-Function Printer With its small footprint, the PEX8605 is ideal for consumer x2 x1 applications. Figure 3 shows a multi-function printer block diagram. The four ports in the PEX8605 provide connectivity between the processor to up to three peripherals each via an x1 PEX 8605 PEX 8605 connection. In this usage model, the PEX8605 provides connectivity to the processor as well as to the various ASICs. x1 x1 x1 x1 x1 Scanner Figure 1. Port Configurations ASIC x1 SerDes Power and Signal Management x1 Processor PEX 8605 x1 The PEX8605 provides low power capability that is fully x1 compliant with the PCI Express power management Eth ASIC specification. In addition, the SerDes physical links can be turned off when unused for even lower power. The PEX8605 Marking supports software control of the SerDes outputs to allow Engine optimization of power and signal strength in a system. The PLX SerDes implementation supports four levels of power off, low, Figure 3. Printer Block Diagram typical, and high. The SerDes block also supports loop-back modes and advanced reporting of error conditions, which Digital TV Tuner enables efficient debug and management of the entire system. An example of a digital TV tuner is shown in Figure 4. In this Port Arbitration and QoS example, the integrated SoC has a single PCIe connection. The The PEX8605 switch supports hardware fixed Round-Robin PEX8605 is used to provide connection to the USB 3.0 endpoint, Ingress Port Arbitration. The PEX8605 also supports Eight a gigabit Ethernet controller and a 3D graphics engine which are Traffic Classes (TCs) as defined in the PCIe specification. used to connect to other consumer peripherals, to a high speed home network and provide advanced graphics respectively. Applications Suitable for fan-out, consumer, control plane applications, and embedded systems, PEX8605 is suited for a wide variety of form SoC factors and applications. x1 Fan-Out The PEX8605 switch, with its flexible configurations, allows PEX 8605 x1 x1 user specific tuning to a variety of host-centric as well as peer- to-peer applications. x1 3D USB3.0 Gbe Engine 2.5 &5 GT/s CPU System x1 Figure 4. Digital TV Tuner Fan-in/out Usage PCIe PCIe PEX 8605 x1 x1 Bandwidth Bridge x1 There are four PCIe lanes available in the PEX8605. Each one can represent an individual port or alternatively two can be PCIe joined to form a x2 port. A x2 port can provide double the bandwidth of a x1 port when all lanes are operating at the same data rates (all at 2.5GT/s or 5.0GT/s). In some instances, the Figure 2. Fan-in/out Usage need to match the bandwidth between devices running at PLX Technology, www.plxtech.com Page 2 of 3 8/17/2011, Version 1.1