Version 1.2 2009 Features PEX 8608 General Features o 8-lane PCI Express switch PEX 8608 - Integrated 5.0 GT/s SerDes o Up to 8 configurable ports 2 o 15 x 15mm , 196-ball PBGA o Typical Power: 1.39 Watts PEX 8608 Key Features PCIe Gen2, 5.0 GT/s 8-lane 8-port PCI Express Switch o Standards Compliant - PCI Express Base Specification r2.0 The ExpressLane PEX 8608 device offers PCI Express switching capability (Backwards compatible with PCIe r1.0a/1.1) enabling users to add scalable high bandwidth non-blocking interconnection to a - PCI Power Management Spec r1.2 wide variety of applications including communications platforms, control plane - Microsoft Vista Compliant applications and embedded systems. The PEX 8608 is well suited for fan-out, - Supports Access Control Services aggregation, peer-to-peer, and intelligent I/O module applications. - Dynamic link-width control - Dynamic SerDes Speed Control Low Packet Latency & High Performance o High Performance The PEX 8608 architecture supports packet cut-thru with a maximum latency of - Non-blocking internal architecture 130ns in x4 to x1 configuration. This, combined with large packet memory and - Full line rate on all ports non-blocking internal switch architecture, provides full line rate on all ports for low- - Cut-Thru latency: 130ns latency applications such as communications and embedded. The low latency - 2KB max payload size - Read Pacing enables applications to achieve high throughput and performance. In addition to low (intelligent bandwidth allocation) latency, the device supports a max payload size of 2048 bytes, enabling the user to - Dual Cast achieve even higher throughout. o Dual-Host & Fail-Over Support - Configurable Non-Transparent port Data Integrity - Moveable upstream port - Crosslink port capability The PEX 8608 provides end-to-end CRC protection (ECRC) and Poison bit support o Flexible Configuration to enable designs that require guaranteed error-free packets. PLX also supports - 8 flexible & configurable ports data path parity and memory (RAM) error correction as packets pass through the (x1 or x4) switch. - Configurable with strapping pins, 2 EEPROM, I C, or Host software Dual-Host and Fail-Over Support - Lane and polarity reversal o PCI Express Power Management The PEX 8608 supports full non-transparent bridging (NTB) functionality to allow - Link power management states: L0, L0s, implementation of multi-host systems and intelligent I/O modules in applications L1, L2/L3 Ready, and L3 which require redundancy support such as communications, storage, and servers. - Device states: D0 and D3 hot o Spread Spectrum Clock Isolation Non-transparent bridges allow systems to isolate host memory domains by - Dual clock domain presenting the processor subsystem as an endpoint rather than another memory o Quality of Service (QoS) system. Base address registers are used to translate addresses doorbell registers are - Two Virtual Channels (VC) per port used to send interrupts between the address domains and scratchpad registers are - Eight Traffic Classes per port accessible from both address domains to allow inter-processor communication. - Weighted Round-Robin Port & VC Arbitration Interoperability o Reliability, Availability, Serviceability 2 - All ports Hot-Plug capable thru I C The PEX 8608 is designed to be fully compliant with the PCI Express Base (Hot-Plug Controller on every port) Specification r2.0 and is backwards compatible to PCI Express Base Specification - ECRC & Poison bit support r1.1 and r1.0a. Additionally each port supports auto-negotiation, lane reversal and - Data path protection polarity reversal. Furthermore, the PEX 8608 is designed for Microsoft Vista - Memory (RAM) error correction compliance. All PLX switches undergo thorough interoperability testing in PLXs - Advanced Error Reporting support Interoperability Lab and compliance testing at the PCI-SIG plug-fest to ensure - Port Status bits and GPIO available - Per port error diagnostics compatibility with PCI Express devices in the market. - Performance monitoring (per port payload & header counters) Device Operation Configuration Flexibility - JTAG AC/DC boundary scan The PEX 8608 provides several ways to configure its operations. The device can be - Fatal Error (FATAL ERR ) output signal 2 configured through strapping pins, I C interface, CPU configuration cycles and/or an - INTA output signal optional serial EEPROM. This allows for easy debug during the development phase and functional monitoring during the operation phase. PLX SerDes implementation supports four levels of power Flexible Port Configurations off, low, typical, and high. The SerDes block also supports The PEX 8608 supports the port configurations as shown in loop-back modes and advanced reporting of error figure 1 below. The figure shows an 8-port configuration, a 5- conditions, which enables efficient debug and management of port configuration as well as a 2-port configuration. the entire system. Port and Virtual Channel (VC) Arbitration The PEX 8608 switch supports hardware fixed and Weighted Round-Robin (WRR) Ingress Port Arbitration. This allows fine tuning of Quality of Service and efficient use of packet buffers for better system performance. The PEX 8608 also supports WRR VC arbitration scheme between the two virtual channels. Applications Suitable for fan-out, control plane applications, embedded systems as well as intelligent I/O and host isolation applications, PEX 8608 can be configured for a wide variety of form factors and applications. Figure 1. Port Configurations Fan-Out Hot-Plug for High Availability The PEX 8608 switch, with its high port count and flexible Hot-Plug capability allows users to replace hardware modules configurations, allows user specific tuning to a variety of host- and perform maintenance without powering down the system. centric as well as peer-to-peer applications. The PEX 8608 Hot-Plug capability feature makes it suitable for High Availability (HA) applications. If the PEX 8608 is used in an application where one or more of its downstream Control Control Memory Memory ports connect to PCI Express slots, each ports Hot-Plug Processor Processor Controller can be used to manage the Hot-Plug event of its associated slot. Every port on the PEX 8608 is equipped with a Hot-Plug control/status register to support Hot-Plug 2 DSPDSPDSPDSP PPEX 8311EX 8311 PCPCIeIe PEPEX 8X 8331111 PCPCIeIe capability through external logic via the I C interface. PCIPCIee PCIPCIee PEPEX 86X 860808 PPEX 86EX 860088 Dual Cast PCIPCI PCIPCI PPEX 8112EX 8112 FPFPGGAA PEPEX 8X 8111122 FPFPGGAA The PEX 8608 supports Dual Cast, a feature which allows for the copying of data (e.g. packets) from one ingress port to two egress ports allowing for higher performance in storage, PCIPCIee PCIPCIee PCIPCIee PCIPCIee security, and mirroring applications. Read Pacing The Read Pacing feature allows users to throttle the amount of Figure 2. Fan-in/out Usage read requests being made by downstream devices. In the case where a downstream device requests several long reads back- Figure 2 shows a typical fan-out design, where the processor to-back, the Root Complex gets tied up in serving this provides a PCI Express link that needs to be fanned into a downstream port. If this port has a narrow link and is therefore larger number of smaller ports for a variety of I/O functions, slow in receiving these read packets from the Root Complex, each with different bandwidth requirements. then other downstream ports may become starved thus, In this example, the PEX 8608 would typically have a 1-lane impacting performance. The Read Pacing feature enhances upstream port, and as many as 7 downstream ports. The performances by allowing for the adequate servicing of all downstream ports provide x1 PCI Express connectivity to the downstream devices by intelligent handling of read requests. endpoints. With its eight ports, the PEX 8608 can provide fan- out connectivity to up to seven PCI Express devices. The SerDes Power and Signal Management figure also shows how some of the ports can be bridged to The PEX 8608 provides low power capability that is fully provide PCI slots or Generic devices through the use of the compliant with the PCI Express power management PEX 8311 and PEX 8112 PCIe bridging devices. specification. In addition, the SerDes physical links can be turned off when unused for even lower power. The PEX 8608 supports software control of the SerDes outputs to allow optimization of power and signal strength in a system. The