Version 1.2 2009 Features PEX 8614 General Features o 12-lane PCI Express switch PEX 8614 - Integrated 5.0 GT/s SerDes o Up to 12 configurable ports 2 o 19 x 19mm , 324-ball HSBGA o Typical Power: 1.74 Watts PEX 8614 Key Features Flexible & Versatile 12-lane 12-port PCI Express Switch o Standards Compliant - PCI Express Base Specification r2.0 (Backwards compatible with PCIe The ExpressLane PEX 8614 device offers PCI Express switching capability r1.0a/1.1) enabling users to add scalable high bandwidth non-blocking interconnection to a - PCI Power Management Spec r1.2 wide variety of applications including control planes, communications platforms, - Microsoft Vista Compliant servers, storage systems and embedded systems. The PEX 8614 is well suited for - Supports Access Control Services fan-out, aggregation, peer-to-peer, and intelligent I/O module applications. - Dynamic link-width control o High Performance Low Packet Latency & High Performance - Non-blocking internal architecture The PEX 8614 architecture supports packet cut-thru with a maximum latency of - Full line rate on all ports - Cut-Thru latency: 140ns 140ns in x4 to x1 configuration. This, combined with large packet memory and - 2KB max payload size non-blocking internal switch architecture, provides full line rate on all ports for low- - Read Pacing latency applications such as communications and servers. The low latency enables (intelligent bandwidth allocation) applications to achieve high throughput and performance. In addition to low latency, - Dual Cast the device supports a max payload size of 2048 bytes, enabling the user to achieve o Dual-Host & Fail-Over Support even higher throughout. - Configurable Non-Transparent port (NTB) Data Integrity - Moveable upstream port The PEX 8614 provides end-to-end CRC protection (ECRC) and Poison bit support - Crosslink port capability to enable designs that require guaranteed error-free packets. PLX also supports o Flexible Configuration data path parity and memory (RAM) error correction as packets pass through the - 12 flexible & configurable ports (x1 or x4) switch. - Configurable with strapping pins, 2 Dual-Host and Fail-Over Support EEPROM, I C, or Host software The PEX 8614 supports full non-transparent bridging (NTB) functionality to allow - Lane and polarity reversal o PCI Express Power Management implementation of multi-host systems and intelligent I/O modules in applications - Link power management states: L0, L0s, which require redundancy support such as communications, storage, and servers. L1, L2/L3 Ready, and L3 Non-transparent bridges allow systems to isolate host memory domains by - Device states: D0 and D3 hot presenting the processor subsystem as an endpoint rather than another memory o Spread Spectrum Clock Isolation - Dual clock domain system. Base address registers are used to translate addresses, doorbell registers are o Quality of Service (QoS) used to send interrupts between the address domains, and scratchpad registers are - Two Virtual Channels (VC) per port accessible from both address domains to allow inter-processor communication. - Eight Traffic Classes per port - Weighted Round-Robin Port & VC Interoperability Arbitration The PEX 8614 is designed to be fully compliant with the PCI Express Base o Reliability, Availability, Serviceability Specification r2.0 and is backwards compatible to PCI Express Base Specification 2 - All ports Hot-Plug capable thru I C r1.1 and r1.0a. Additionally each port supports auto-negotiation, lane reversal and (Hot-Plug Controller on every port) polarity reversal. Furthermore, the PEX 8614 is designed for Microsoft Vista - ECRC & Poison bit support compliance. All PLX switches undergo thorough interoperability testing in PLXs - Data path protection Interoperability Lab and compliance testing at the PCI-SIG plug-fest to ensure - Memory (RAM) error correction - Advanced Error Reporting support compatibility with PCI Express devices in the market. - Port Status bits and GPIO available Device Operation Configuration Flexibility - Per port error diagnostics The PEX 8614 provides several ways to configure its operations. The device can be - Performance monitoring 2 (per port payload & header counters) configured through strapping pins, I C interface, CPU configuration cycles and/or an - JTAG AC/DC boundary scan optional serial EEPROM. This allows for easy debug during the development phase - Fatal Error (FATAL ERR ) output signal and functional monitoring during the operation phase. - INTA output signal off, low, typical, and high. The SerDes block also supports Flexible Port Configurations loop-back modes and advanced reporting of error The PEX 8614 flexible architecture supports a number of port conditions, which enables efficient debug and management of configurations as required by the target applications as shown the entire system. in figure 1 below. Port and Virtual Channel (VC) Arbitration The PEX 8614 switch supports hardware fixed and Weighted Round-Robin Ingress Port Arbitration. This allows fine tuning of Quality of Service and efficient use of packet buffers for better system performance. The PEX 8614 also supports WRR VC arbitration scheme between the two virtual channels. Applications Suitable for fan-out, control plane applications, embedded systems as well as intelligent I/O applications, PEX 8614 can be configured for a wide variety of form factors and applications. Figure 1. Port Configurations Fan-Out The PEX 8614 switch, with its high port count and flexible configurations, allows user specific tuning to a variety of host- Hot-Plug for High Availability centric as well as peer-to-peer applications. Hot-Plug capability allows users to replace hardware modules and perform maintenance without powering down the system. The PEX 8614 Hot-Plug capability feature makes it suitable for High Availability (HA) applications. If the PEX 8614 is Control Control Memory Memory used in an application where one or more of its downstream Processor Processor ports connect to PCI Express slots, each ports Hot-Plug Controller can be used to manage the Hot-Plug event of its FPGAFPGAFPGAFPGA PEX 831PEX 831PEX 83PEX 83111111 associated slot. Every port on the PEX 8614 is equipped with a Hot-Plug control/status register to support Hot-Plug PCIePCIe PCIePCIe 2 capability through external logic via the I C interface. PCPCPCPCIIII PEX 811PEX 81122 PEX 81PEX 811212 PCPCIIee PCPCIIee PEX 86PEX 861414 PEX 86PEX 861414 Dual Cast FPGAFPGA FPGAFPGA The PEX 8614 supports Dual Cast, a feature which allows for DSPDSP DSPDSP PEX 831PEX 83111 PEX 83PEX 831111 the copying of data (e.g. packets) from one ingress port to two egress ports allowing for higher performance in storage, security, and mirroring applications. PCIPCIee PCPCIeIe PCIPCIee PCPCIeIe Read Pacing Figure 2. Fan-in/out Usage The Read Pacing feature allows users to throttle the amount of read requests being made by downstream devices. In the case Figure 2 shows a typical fan-out design, where the processor where a downstream device requests several long reads back- provides a PCI Express link that needs to be fanned into a to-back, the Root Complex gets tied up in serving this larger number of smaller ports for a variety of I/O functions, downstream port. If this port has a narrow link and is therefore each with different bandwidth requirements. slow in receiving these read packets from the Root Complex, In this example, the PEX 8614 would typically have a 1-lane then other downstream ports may become starved thus, upstream port, and as many as 11 downstream ports. The impacting performance. The Read Pacing feature enhances downstream ports provide x1 PCI Express connectivity to the performances by allowing for the adequate servicing of all endpoints. With its twelve ports, the PEX 8614 can provide downstream devices by intelligent handling of read requests. fan-out connectivity to up to eleven PCI Express devices. The figure also shows how some of the ports can be bridged to SerDes Power and Signal Management provide PCI slots or Generic devices through the use of the The PEX 8614 provides low power capability that is fully PEX 8311 and PEX 8112 PCIe bridging devices. compliant with the PCI Express power management specification. In addition, the SerDes physical links can be Control Plane Application turned off when unused for even lower power. The PEX 8614 The PEX 8614 is ideal for control planes in routers and other supports software control of the SerDes outputs to allow communications sub-systems to meet increased packet optimization of power and signal strength in a system. The processing needs without compromising latency. Figure 3 PLX SerDes implementation supports four levels of power