Version 1.0 2009 PEX 8616 Features Features PE PEXX 8618616 V6 Viittaals ls oo 16-lane, 4-por16-lane, 4-port Pt PCCIe Gen2Ie Gen2 switch switch -- IntegratedIntegrated 5.0 5.0 GT/s SerDes GT/s SerDes 22 PCIe Gen2, 5.0GT/s 16-lane, 4- 4-porport Switch t Switch oo 19 x 19mm19 x 19mm , 32, 324-pin FCBGA packag4-pin FCBGA package e oo TyTyppiical Power: cal Power: 1.7 Watts 1.7 Watts TM The ExpressLane PEX 8616 device offers PCI Express switching capability enabling users to add scalable high bandwidth, non-blocking PE PEXX 8618616 Key6 Key Fea Feattures ures interconnection to a wide variety of applications including oo StandarStandardds Compliant s Compliant workstations, storage systems, communications platforms, -- PCI Express BasPCI Express Basee Specification, r Specification, r2.0 2.0 (backwards(backwards comcomppatiblatiblee w/ w/ P PCCIe rIe r11.0a/1.0a/1..1)1) embedded systems, and intelligent I/O modules. The PEX 8616 is -- PCI Power Management Spec, rPCI Power Management Spec, r1.21.2 well suited for fan-out, aggregation, and peer-to-peer applications. -- Microsoft Vista Microsoft Vista Compliant Compliant -- Supports Access ControlSupports Access Control Servic Serviceess -- DDyynamic link-width connamic link-width conttrol rol High Performance & Low Packet Latency -- DDyynamnamiicc S SeerDesrDes s sppeed eed controcontroll The PEX 8616 architecture supports packet cut-thru with a maximum oo HighHigh P Perforerformamannce ce latency of 170ns (x4 to x4). This, combined with large packet memory and -- Non-blocking sNon-blocking swwitch fitch faabric bric non-blocking internal switch architecture, provides full line rate on all ports -- Full linFull line re raattee on on allall ports ports for performance-hungry applications such as servers and switch fabrics. -- Packet Cut-ThruPacket Cut-Thru w with 170ns maxith 170ns max pack packet et latlateencncy (x4y (x4 to to x4 x4) ) The low latency enables applications to achieve high throughput and -- 2KB Max Pay2KB Max Payllooaad Size d Size performance. In addition to low latency, the device supports a max payload -- Read PaRead Pacingcing (ba (bandwidth throndwidth throttlttlining) g) size of 2048 bytes, enabling the user to achieve even higher throughput. -- Dual-CasDual-Castt oo FlexiblFlexiblee Config Configuration uration -- Ports configurabPorts configurable le as x1, x2, x4, as x1, x2, x4, x8 x8 Data Integrity -- Registers Registers configconfigurable withurable with strap strappping ing The PEX 8616 provides end-to-end CRC (ECRC) protection and Poison bit 22 pins, EEPROM, pins, EEPROM, II C, orC, or host software host software support to enable designs that require end-to-end data integrity. PLX also -- Lane andLane and polar polarityity reversreversal al supports data path parity and memory (RAM) error correction as packets -- ComComppatibleatible with with PCIe 1 PCIe 1..0a PM0a PM pass through the switch. oo Dual-Host & Fail-OverDual-Host & Fail-Over Suppor Supportt -- Configurable NoConfigurable Non-Transparenn-Transparent pt poort rt -- Moveable upstream port Moveable upstream port Flexible Register & Port Configuration -- Crosslink port Crosslink port capability capability The PEX 8616s 4 ports can be configured to lane widths of x1, x2, x4, or oo QuQualitality ofy of S Serviervice (ce (QoSQoS) ) x8. Flexible buffer allocation, along with the device s flexible packet flow -- Eight traffEight traffiic clasc classes per porses per port t control, maximizes throughput for applications where more traffic flows in -- Weighted rouWeighted round-nd-robin source robin source port arbport arbitraitrationtion the downstream, rather than upstream, direction. Any port can be designated oo ReliabilitReliability, Avay, Availabilitilability, Sey, Servicrviceabiliteabilityy as the upstream port, which can be changed dynamically. The PEX 8616 also -- 2 Hot Plug Ports2 Hot Plug Ports with n with naativtive HP e HP Signals Signals 22 provides several ways to -- All ports hoAll ports hot pt plluugg cap capablablee thru thru I I C C x8x8 x4x4 configure its registers. (Hot Plug Contr(Hot Plug Controollerller on on evereveryy poport) rt) -- ECRC andECRC and Poison bit support Poison bit support The device can be -- Data PaData Path pth paaritrityy configured through -- MemoryMemory (RAM) Error (RAM) Error Correctio Correction n 2 PEX 8616PEX 8616PEX 8616PEX 8PEX 8PEX 8616616616 strapping pins, I C PEX 861PEX 861PEX 861666 PEX 8616PEX 8616PEX 8616 -- INTA and FATAL ERR signals INTA and FATAL ERR signals interface, host software, -- Advanced ErrorAdvanced Error Reporting Reporting -- PPoort Srt Sttatusatus b bitsits a and GPnd GPIO avaiIO availablabllee or an optional serial -- Per port Per port errorerror diagnostics diagnostics EEPROM. This allows for x4x4 xx44 x4x4 x4x4 xx44 -- Performance MoPerformance Monitoringnitoring easy debug during the Per port pPer port paayyllooaadd & h & headeader er counters counters development phase, x8 x4x4 performance monitoring NT during the operation phase, and driver or PEX 8PEX 8616616 PEX 86PEX 861616 PEX 861PEX 861PEX 861666 PEX 8616PEX 8616PEX 8616 software upgrade. Figure 1 shows some of the PEX 8616s common port x8 x4x4 x2x2 xx22 configurations. Figure 1. Common Port ConfigurationsDual-Host & Failover Support its associated slot. Every port on the PEX 8616 is The PEX 8616 product supports a Non-Transparent equipped with a hot-plug control/status register to (NT) Port, which enables the implementation of multi- support hot-plug capability through external logic via the 2 I host systems and intelligent I/O modules in storage, C interface. communications, and blade server applications. The NT port allows systems to isolate host memory domains by SerDes Power and Signal Management presenting the processor subsystem as an endpoint rather The PEX 8616 supports software control of the SerDes than another memory outputs to allow optimization of power and signal PrPrPrPrPrPrPrPrimimimimimimimimaaaaaaaarrrrrrrry Hosty Hosty Hosty Hosty Hosty Hosty Hosty Host SSSSSSSSeeeeeeeecondacondacondacondacondacondacondacondarrrrrrrryyyyyyyy Host Host Host Host H H H Hostostostost system. Base address strength in a system. The PLX SerDes implementation CPUCPUCPUCPU CPUCPUCPUCPU CPUCPUCPUCPU CPUCPUCPUCPU registers are used to supports four levels of power off, low, typical, and translate addresses high. The SerDes block also supports loop-back modes doorbell registers are Root Root Root Root Root Root Root Root and advanced reporting of error conditions, which ComComComComComComComCompppppppplllllllleeeeeeeexxxxxxxx used to send enables efficient management of the entire system. interrupts between the address domains and Interoperability NTNTNT scratchpad registers The PEX 8616 is designed to be fully compliant with the PPPPEX 8616PEX 8616PEX 8616EX 86EX 86EX 86161616 Non-TransparentNon-TransparentNon-Transparent (accessible by both PCI Express Base Specification r2.0, and is backwards PortPortPort CPUs) allow inter- compatible to PCI Express Base Specification r1.1 and processor r1.0a. Additionally, it supports auto-negotiation, lane End End End End EnEnEnEndddd End End End End EnEnEnEndddd PointPointPointPoint PointPointPointPoint PointPointPointPoint PointPointPointPoint communication reversal, and polarity reversal. Furthermore, the (see Figure 2). PEX 8616 is designed for Microsoft Vista compliance. FigureFigure 2.2. Non-Tran Non-Transparent Porsparent Portt In a two-port configuration (as in Figure 1), the All PLX switches undergo thorough interoperability PEX 8616 can serve as an NT buffer, isolating two host testing in PLXs Interoperability Lab and compliance domains via two x8 links. testing at the PCI-SIG plug-fest. Dual Cast The PEX 8616 supports Dual Cast, a feature which allows for the copying of data (e.g. packets) from one Applications ingress port to two egress ports allowing for higher Suitable for host-centric as well as peer-to-peer traffic performance in dual-graphics, storage, security, and patterns, the PEX 8616 can be configured for a broad redundant applications. range of form factors and applications. Read Pacing Host Centric Fan-out The Read Pacing feature allows users to throttle the The PEX 8616, with its symmetric or asymmetric lane amount of read requests being made by downstream configuration capability, allows user-specific tuning to a devices. When a downstream device requests several variety of host-centric applications. Figure 3 shows a long reads back-to-back, the Root Complex gets tied up typical workstation design where the root complex in serving this downstream port. If this port has a narrow provides a PCI Express link that needs to be expanded to link and is therefore slow in receiving these read packets a larger number of smaller ports for a variety of I/O from the Root Complex, then other downstream ports functions. In this example, the PEX 8616 has a 4-lane may become starved thus, impacting performance. The upstream port and three downstream ports using x4 Read Pacing feature enhances performances by allowing links. for the adequate servicing of all downstream devices. The PEX 8616 can also be used to create PCIe Gen1 (2.5 Hot Plug for High Availability Gbps) ports. The PEX 8616 is backwards compatible Hot plug capability allows users to replace hardware with PCIe Gen1 devices. Therefore, the PEX 8616 modules and perform maintenance without powering enables a Gen 2 native Chip Set to fan-out to Gen 1 down the system. The PEX 8616 hot plug capability endpoints. In Figure 3, the PCIe slots connected to the feature makes it suitable for High Availability (HA) PEX 8616s downstream ports can be populated with applications. Two downstream ports include a Standard either PCIe Gen1 or PCIe Gen 2 devices. Conversely, Hot Plug Controller. If the PEX 8616 is used in an the PEX 8616 can also be used to create Gen 2 ports on application where one or more of its downstream ports a Gen 1 native Chip Set in the same fashion. connect to PCI Express slots, each ports Hot Plug Controller can be used to manage the hot-plug event of