Version 1.2 2009 Features PEX 8618 General Features o 16-lane PCI Express switch PEX 8618 - Integrated 5.0 GT/s SerDes o Up to 16 configurable ports 2 o 19 x 19mm , 324-ball HSBGA o Typical Power: 1.93 Watts PEX 8618 Key Features Flexible & Versatile 16-lane 16-port PCI Express Switch o Standards Compliant - PCI Express Base Specification r2.0 (Backwards compatible with PCIe The ExpressLane PEX 8618 device offers PCI Express switching capability r1.0a/1.1) enabling users to add scalable high bandwidth non-blocking interconnection to a - PCI Power Management Spec r1.2 wide variety of applications including control planes, communication platforms, - Microsoft Vista Compliant servers, storage systems and embedded systems. The PEX 8618 is well suited for - Supports Access Control Services fan-out, aggregation, peer-to-peer, and intelligent I/O module applications. - Dynamic link-width control o High Performance Low Packet Latency & High Performance - Non-blocking internal architecture The PEX 8618 architecture supports packet cut-thru with a maximum latency of - Full line rate on all ports - Cut-Thru latency: 140ns 140ns. This, combined with large packet memory and non-blocking internal switch - 2KB max payload size architecture, provides full line rate on all ports for low-latency applications such as - Read Pacing communications and servers. The low latency enables applications to achieve high (intelligent bandwidth allocation) throughput and performance. In addition to low latency, the device supports a max - Dual Cast payload size of 2048 bytes, enabling the user to achieve even higher throughout. o Dual-Host & Fail-Over Support - Configurable Non-Transparent port Data Integrity (NTB) The PEX 8618 provides end-to-end CRC protection (ECRC) and Poison bit support - Moveable upstream port to enable designs that require guaranteed error-free packets. PLX also supports - Crosslink port capability data path parity and memory (RAM) error correction as packets pass through the o Flexible Configuration switch. - 16 flexible & configurable ports (x1, x4, or x8) Dual-Host and Fail-Over Support - Configurable with strapping pins, 2 The PEX 8618 supports full non-transparent bridging (NTB) functionality to allow EEPROM, I C, or Host software implementation of multi-host systems and intelligent I/O modules in applications - Lane and polarity reversal o PCI Express Power Management which require redundancy support such as communications, storage, and servers. - Link power management states: L0, L0s, Non-transparent bridges allow systems to isolate host memory domains by L1, L2/L3 Ready, and L3 presenting the processor subsystem as an endpoint rather than another memory - Device states: D0 and D3 hot system. Base address registers are used to translate addresses doorbell registers are o Spread Spectrum Clock Isolation - Dual clock domain used to send interrupts between the address domains and scratchpad registers are o Quality of Service (QoS) accessible from both address domains to allow inter-processor communication. - Two Virtual Channels (VC) per port - Eight Traffic Classes per port Interoperability - Weighted Round-Robin Port & VC The PEX 8618 is designed to be fully compliant with the PCI Express Base Arbitration Specification r2.0 and is backwards compatible to PCI Express Base Specification o Reliability, Availability, Serviceability r1.1 and r1.0a. Additionally each port supports auto-negotiation, lane reversal and 2 - All ports Hot-Plug capable thru I C polarity reversal. Furthermore, the PEX 8618 is designed for Microsoft Vista (Hot-Plug Controller on every port) compliance. All PLX switches undergo thorough interoperability testing in PLXs - ECRC & Poison bit support Interoperability Lab and compliance testing at the PCI-SIG plug-fest to ensure - Data path protection compatibility with PCI Express devices in the market. - Memory (RAM) error correction - Advanced Error Reporting support Device Operation Configuration Flexibility - Port Status bits and GPIO available The PEX 8618 provides several ways to configure its operations. The device can be - Per port error diagnostics 2 configured through strapping pins, I C interface, CPU configuration cycles and/or an - Performance monitoring (per port payload & header counters) optional serial EEPROM. This allows for easy debug during the development phase - JTAG AC/DC boundary scan and functional monitoring during the operation phase. - Fatal Error (FATAL ERR ) output signal - INTA output signal off, low, typical, and high. The SerDes block also supports Flexible Port Configurations loop-back modes and advanced reporting of error The PEX 8618 supports a large number of port configurations conditions, which enables efficient debug and management of as shown in figure 1 below. Please refer to the PEX 8618 the entire system. datasheet for more port configuration options. Port and Virtual Channel (VC) Arbitration x1x1 x4x4 x8x8 The PEX 8618 switch supports hardware fixed and Weighted x1x1 Round-Robin Ingress Port Arbitration. This allows fine tuning x1x1 PEXPEXPEX 86 86 86111888 x1x1 PEX 86PEX 86PEX 86111888 x1x1 x1x1 PEX 86PEX 86PEX 86111888 x1x1 PEX 86PEX 86PEX 86111888 PEX 8618PEX 8618PEX 8618 PEXPEXPEX 86 86 86111888 of Quality of Service and efficient use of packet buffers for x1x1 x1x1 x1x1 x1x1 better system performance. The PEX 8618 also supports WRR VC arbitration scheme between the two virtual channels. 1515 x1 x1 PoPortsrts xx11xx11x1xx1x1x1x1x1x11 x1xx1x1x1x11x1x1 x4x4 x4x4 x8x8 Applications x1x1 Suitable for fan-out, control plane applications, embedded x4x4 x1x1 PEX 86PEX 86PEX 86PEX 86PEX 86PEX 86111111888888 PEPEPEX 86X 86X 86111888 PEX 86PEX 86PEX 86111888 PEX 86PEX 86PEX 86111888 PEX 86PEX 86PEX 86111888 systems as well as intelligent I/O applications, PEX 8618 x1x1 can be configured for a wide variety of form factors and applications. x4x4 x4x4 x4x4 x4x4 x4x4 xx11xx11x1xx1x1x11x1 Figure 1. Port Configurations Fan-Out The PEX 8618 switch, with its high port count and flexible configurations, allows user specific tuning to a variety of host- Hot-Plug for High Availability centric as well as peer-to-peer applications. Hot-Plug capability allows users to replace hardware modules and perform maintenance without powering down the system. CoContntrrooll CoContntrrooll MemMemMemMemooooryryryry The PEX 8618 Hot-Plug capability feature makes it suitable ProcesProcesProcesProcessorsorsorsor for High Availability (HA) applications. If the PEX 8618 is used in an application where one or more of its downstream ports connect to PCI Express slots, each ports Hot-Plug x1x1x1x1 Controller can be used to manage the hot-plug Hot-Plug event of its associated slot. Every port on the PEX 8618 is equipped PCIePCIePCIePCIe PCPCPCPCIIII with a Hot-Plug control/status register to support Hot-Plug PPPPEX 8PEX 8PEX 8EEEXXX 81 81 81111121212111222 2 capability through external logic via the I C interface. PCPCPCPCIIIIeeee PEX 8618PEX 8618PEX 8618 FPFPGAGA PEPEPEX 8X 8X 8666181818 FPFPGAGA PPPEEEXXX 83 83 83111111 PEX 8PEX 8PEX 8333111111 Dual Cast PCPCIeIe PCPCIeIe PCIPCI PCIPCI PEPEPEPEX 8PEX 8PEX 8X 8X 8X 8111111111111222222 The PEX 8618 supports Dual Cast, a feature which allows for the copying of data (e.g. packets) from one ingress port to two egress ports allowing for higher performance in storage, security, and mirroring applications . PCPCPCPCIIIIeeee PCPCIIee PCPCIeIe PCPCIeIe PCPCIIee PCPCIeIe PCPCIeIe Read Pacing Figure 2. Fan-in/out Usage The Read Pacing feature allows users to throttle the amount of read requests being made by downstream devices. In the case Figure 2 shows a typical fan-out design, where the processor where a downstream device requests several long reads back- provides a PCI Express link that needs to be fanned into a to-back, the Root Complex gets tied up in serving this larger number of smaller ports for a variety of I/O functions, downstream port. If this port has a narrow link and is therefore each with different bandwidth requirements. slow in receiving these read packets from the Root Complex, In this example, the PEX 8618 would typically have a 1-lane then other downstream ports may become starved thus, upstream port, and as many as 15 downstream ports. The impacting performance. The Read Pacing feature enhances downstream ports provide x1 PCI Express connectivity to the performances by allowing for the adequate servicing of all endpoints. With its sixteen ports, the PEX 8618 can provide downstream devices by intelligent handling of read requests. fan-out connectivity to up to fifteen PCI Express devices. The figure also shows how some of the ports can be bridged to SerDes Power and Signal Management provide PCI slots or Generic devices through the use of the The PEX 8618 provides low power capability that is fully PEX 8311 and PEX 8112 PCIe bridging devices. compliant with the PCI Express power management specification. In addition, the SerDes physical links can be Control Plane Application turned off when unused for even lower power. The PEX 8618 The PEX 8618 is ideal for control planes in routers and other supports software control of the SerDes outputs to allow communications sub-systems to meet increased packet optimization of power and signal strength in a system. The processing needs without compromising latency. Figure 3 PLX SerDes implementation supports four levels of power