Version 1.0 2009 PEX 8624 Features Features PE PEXX 8628624 V4 Viittaals ls oo 24-lane, 6-por24-lane, 6-port Pt PCCIe Gen2Ie Gen2 switch switch -- IntegratedIntegrated 5.0 5.0 GT/s SerDes GT/s SerDes PCIe Gen2, 5.0GT/s 24-lane, 6- 6-porport Switch t Switch 22 oo 19 x 19mm19 x 19mm , 32, 324-pin FCBGA packag4-pin FCBGA package e oo TyTyppiical Power: cal Power: 1.9 Watts 1.9 Watts TM The ExpressLane PEX 8624 device offers PCI Express switching capability enabling users to add scalable high bandwidth, non-blocking PE PEXX 8628624 Key4 Key Fea Feattures ures interconnection to a wide variety of applications including oo StandarStandardds Compliant s Compliant workstations, storage systems, and communications platforms. The -- PCI Express BasPCI Express Basee Specification, r Specification, r2.0 2.0 (backwards(backwards comcomppatiblatiblee w/ w/ P PCCIe rIe r11.0a/1.0a/1..1)1) PEX 8624 is well suited for fan-out, aggregation, and peer-to-peer -- PCI Power Management Spec, rPCI Power Management Spec, r1.21.2 applications. -- Microsoft Vista Microsoft Vista Compliant Compliant -- Supports Access ControlSupports Access Control Servic Serviceess -- DDyynamic link-width connamic link-width conttrol rol High Performance & Low Packet Latency -- DDyynamnamiicc S SeerDesrDes s sppeed eed controcontroll The PEX 8624 architecture supports packet cut-thru with a maximum oo HighHigh P Perforerformamannce ce latency of 160ns (x8 to x8). This, combined with large packet memory and -- Non-blocking sNon-blocking swwitch fitch faabric bric non-blocking internal switch architecture, provides full line rate on all ports -- Full linFull line re raattee on on allall ports ports for performance-hungry applications such as servers and switch fabrics. -- Packet Cut-ThruPacket Cut-Thru w with 160ns maxith 160ns max pack packet et latlateencncy (x8y (x8 to to x8 x8) ) The low latency enables applications to achieve high throughput and -- 2KB Max Pay2KB Max Payllooaad Size d Size performance. In addition to low latency, the device supports a max payload -- Read PaRead Pacingcing (ba (bandwidth throndwidth throttlttlining) g) size of 2048 bytes, enabling the user to achieve even higher throughput. -- Dual-CasDual-Castt oo FlexiblFlexiblee Config Configuration uration -- Ports configurabPorts configurable le as x1, x2, x4, as x1, x2, x4, x8 x8 Data Integrity -- Registers Registers configconfigurable withurable with strap strappping ing The PEX 8624 provides end-to-end CRC (ECRC) protection and Poison bit 22 pins, EEPROM, pins, EEPROM, II C, orC, or host software host software support to enable designs that require end-to-end data integrity. PLX also -- Lane andLane and polar polarityity reversreversal al supports data path parity and memory (RAM) error correction as packets -- ComComppatibleatible with with PCIe 1 PCIe 1..0a PM0a PM pass through the switch. oo Dual-Host & Fail-OverDual-Host & Fail-Over Suppor Supportt -- Configurable NoConfigurable Non-Transparenn-Transparent pt poort rt -- Moveable upstream port Moveable upstream port Flexible Register & Port Configuration -- Crosslink port Crosslink port capability capability The PEX 8624s 6 ports can be configured to lane widths of x1, x2, x4, or oo QuQualitality ofy of S Serviervice (ce (QoSQoS) ) x8. Flexible buffer allocation, along with the device s flexible packet flow -- Eight traffEight traffiic clasc classes per porses per port t control, maximizes throughput for applications where more traffic flows in -- Weighted rouWeighted round-nd-robin source robin source port arbport arbitraitrationtion the downstream, rather than upstream, direction. Any port can be designated oo ReliabilitReliability, Avay, Availabilitilability, Sey, Servicrviceabiliteabilityy as the upstream port, which -- 3 Hot Plug Ports3 Hot Plug Ports with n with naativtive HP e HP Signals Signals x4 22 can be changed dynamically. x8 -- All ports hoAll ports hot pt plluugg cap capablablee thru thru I I C C The PEX 8624 also provides (Hot Plug Contr(Hot Plug Controollerller on on evereveryy poport) rt) -- ECRC andECRC and Poison bit support Poison bit support several ways to configure its -- Data PaData Path pth paaritrityy registers. The device can be PEX 8PEX 8PEX 8624PEX 8624624624 PEX 8PEX 8624624 PEXPEX 862 86244 -- MemoryMemory (RAM) Error (RAM) Error Correctio Correction n configured through strapping -- INTA and FATAL ERR signals INTA and FATAL ERR signals 2 pins, I C interface, host -- Advanced ErrorAdvanced Error Reporting Reporting -- PPoort Srt Sttatusatus b bitsits a and GPnd GPIO avaiIO availablabllee software, or an optional 5 x4 x4 x4 x4 x4 -- Per port Per port errorerror diagnostics diagnostics serial EEPROM. This allows -- Performance MoPerformance Monitoringnitoring x8 for easy debug during the x8 Per port pPer port paayyllooaadd & h & headeader er counters counters development phase, performance monitoring during the operation phase, PEX 8PEX 8624624 PEX 8PEX 8PEPEX 862X 86262462444 PEXPEX 862 86244 and driver or software upgrade. Figure 1 shows some of the PEX 8624s x8 x4 x4 x8 x8 common port configurations. Figure 1. Common Port Configurations Dual-Host & Failover Support ports connect to PCI Express slots, each ports Hot Plug The PEX 8624 product supports a Non-Transparent Controller can be used to manage the hot-plug event of (NT) Port, which enables the implementation of multi- its associated slot. Every port on the PEX 8624 is host systems in communications, storage, and blade equipped with a hot-plug control/status register to server applications. The NT port allows systems to support hot-plug capability through external logic via the 2 isolate host memory domains by presenting the I C interface. processor subsystem as an endpoint rather than another memory system. Base address registers are used to SerDes Power and Signal Management translate addresses doorbell registers are used to send The PEX 8624 supports software control of the SerDes interrupts between the address domains and scratchpad outputs to allow optimization of power and signal registers (accessible by both CPUs) allow inter- strength in a system. The PLX SerDes implementation processor communication (see Figure 2). supports four levels of power off, low, typical, and high. The SerDes block also supports loop-back modes PrPrPrPriPriPriiiimmmmmmary Hary Hary Haryaryary Ho Ho Hoooostststststst SeconSeconSeconSeSeSecondacondacondadddary Hary Hary Hrrryyy H H Hoooostostostsssttt and advanced reporting of error conditions, which CPUCPUCPU CPCPCPUUU CPUCPUCPU CPCPCPUUU enables efficient management of the entire system. Interoperability Root Root Root Root Root Root CompleCompleCompleCompleCompleComplexxxxxx The PEX 8624 is designed to be fully compliant with the PCI Express Base Specification r2.0, and is backwards compatible to PCI Express Base Specification r1.1 and NTNT r1.0a. Additionally, it supports auto-negotiation, lane PEX 8624PEX 8624 PEPEX 8X 8624624 NNon-Transparenton-Transparent reversal, and polarity reversal. Furthermore, the PoPortrt PEX 8624 is designed for Microsoft Vista compliance. EEEEnd nd nd nd End End End End End End End End EEEEnd nd nd nd End End End End End End End End All PLX switches undergo thorough interoperability PointPointPointPoint PoiPoiPoiPoinnnntttt PointPointPointPoint PointPointPointPoint PoiPoiPoiPoinnnntttt PointPointPointPoint testing in PLXs Interoperability Lab and compliance FigurFiguree 2. 2. Non Non--TTrransansppararenent t PorPortt testing at the PCI-SIG plug-fest. Dual Cast The PEX 8624 supports Dual Cast, a feature which allows for the copying of data (e.g. packets) from one Applications ingress port to two egress ports allowing for higher Suitable for host-centric as well as peer-to-peer traffic performance in dual-graphics, storage, security, and patterns, the PEX 8624 can be configured for a broad redundant applications. range of form factors and applications. Read Pacing Host Centric Fan-out The Read Pacing feature allows users to throttle the The PEX 8624, with its symmetric or asymmetric lane amount of read requests being made by downstream configuration capability, allows user-specific tuning to a devices. When a downstream device requests several variety of host-centric applications. Figure 3 shows a long reads back-to-back, the Root Complex gets tied up typical workstation design where the root complex in serving this downstream port. If this port has a narrow provides a PCI Express link that needs to be expanded to link and is therefore slow in receiving these read packets a larger number of smaller ports for a variety of I/O from the Root Complex, then other downstream ports functions. In this example, the PEX 8624 has an 8-lane may become starved thus, impacting performance. The upstream port, and four downstream ports using x4 links. Read Pacing feature enhances performances by allowing for the adequate servicing of all downstream devices. The PEX 8624 can also be used to create PCIe Gen1 (2.5 Gbps) ports. The PEX 8624 is backwards compatible Hot Plug for High Availability with PCIe Gen1 devices. Therefore, the PEX 8624 Hot plug capability allows users to replace hardware enables a Gen 2 native Chip Set to fan-out to Gen 1 modules and perform maintenance without powering endpoints. In Figure 3, the PCIe slots connected to the down the system. The PEX 8624 hot plug capability PEX 8624s downstream ports can be populated with feature makes it suitable for High Availability (HA) either PCIe Gen1 or PCIe Gen 2 devices. Conversely, applications. Three downstream ports include a the PEX 8624 can also be used to create Gen 2 ports on Standard Hot Plug Controller. If the PEX 8624 is used in a Gen 1 native Chip Set in the same fashion. an application where one or more of its downstream