Version 1.0 2009
PEX 8632
Features
PEX 8632 Vitals
o 32-lane, 12-port PCIe Gen2 switch
- Integrated 5.0 GT/s SerDes
2 PCIe Gen2, 5.0GT/s 32-lane, 12-port Switch
o 27 x 27mm , 676-pin FCBGA package
o Typical Power: 2.7 Watts
TM
The ExpressLane PEX 8632 device offers PCI Express switching
capability enabling users to add scalable high bandwidth, non-blocking
PEX 8632 Key Features
interconnection to a wide variety of applications including servers,
o Standards Compliant
storage systems, and communications platforms. The PEX 8632 is
- PCI Express Base Specification, r2.0
(backwards compatible w/ PCIe r1.0a/1.1)
well suited for fan-out, aggregation, and peer-to-peer applications.
- PCI Power Management Spec, r1.2
- Microsoft Vista Compliant
High Performance & Low Packet Latency
- Supports Access Control Services
The PEX 8632 architecture supports packet cut-thru with a maximum
- Dynamic link-width control
- Dynamic SerDes speed control
latency of 160ns (x8 to x8). This, combined with large packet memory and
o High Performance
non-blocking internal switch architecture, provides full line rate on all ports
- Non-blocking switch fabric
for performance-hungry applications such as servers and switch fabrics.
- Full line rate on all ports
The low latency enables applications to achieve high throughput and
- Packet Cut-Thru with 160ns max packet
latency (x8 to x8) performance. In addition to low latency, the device supports a max payload
- 2KB Max Payload Size
size of 2048 bytes, enabling the user to achieve even higher throughput.
- Read Pacing (bandwidth throttling)
- Dual-Cast
Data Integrity
o Flexible Configuration
The PEX 8632 provides end-to-end CRC (ECRC) protection and Poison bit
- Ports configurable as x1, x2, x4, x8, x16
- Registers configurable with strapping
support to enable designs that require end-to-end data integrity. PLX also
2
pins, EEPROM, I C, or host software
supports data path parity and memory (RAM) error correction as packets
- Lane and polarity reversal
pass through the switch.
- Compatible with PCIe 1.0a PM
o Dual-Host & Fail-Over Support
- Configurable Non-Transparent port Flexible Register & Port Configuration
- Moveable upstream port
The PEX 8632s 12 ports can be configured to lane widths of x1, x2, x4, x8,
- Crosslink port capability
or x16. Flexible buffer allocation, along with the device's flexible packet
o Quality of Service (QoS)
flow control, maximizes throughput for applications where more traffic
- Eight traffic classes per port
flows in the downstream, rather than upstream, direction. Any port can be
- Weighted round-robin source
port arbitration
designated as the upstream port, which can be changed dynamically. The
o Reliability, Availability, Serviceability
PEX 8632 also provides
- 3 Hot Plug Ports with native HP Signals
x4x4
several ways to configure x8x8
2
- All ports hot plug capable thru I C
its registers. The device
(Hot Plug Controller on every port)
can be configured
- ECRC and Poison bit support
- Data Path parity
through strapping pins,
PPPEEEXXX 8632 8632 8632
PEPEPEX 8632X 8632X 8632 PPPEEEXXX 8632 8632 8632
PEPEPEX 8632X 8632X 8632
- Memory (RAM) Error Correction 2
I C interface, host
- INTA# and FATAL_ERR# signals
software, or an optional
- Advanced Error Reporting
serial EEPROM. This
- Port Status bits and GPIO available
3 x3 x44 8 x28 x2
2 x82 x8 2 x42 x4
- Per port error diagnostics
allows for easy debug
- Performance Monitoring
during the development
x16x16
x8x8
Per port payload & header counters
phase, performance
monitoring during the
operation phase, and
PPPPEPEPEEEEXXXX 8632X 8632X 8632 8632 8632 8632
PEPEPEX 8X 8X 8632632632
PPPEEEXXX 8632 8632 8632
driver or software
upgrade. Figure 1 shows
some of the PEX 8632s
common port
10 x210 x2 x8x8 x8x8
configurations.
Figure 1. Common Port ConfigurationsDual-Host & Failover Support support hot-plug capability through external logic via the
2
The PEX 8632 product supports a Non-Transparent I C interface.
(NT) Port, which enables the implementation of multi-
host systems in communications, storage, and blade SerDes Power and Signal Management
server applications. The NT port allows systems to The PEX 8632 supports software control of the SerDes
isolate host memory outputs to allow optimization of power and signal
PPPrrriiimmmarararyyy H H Hoooststst SSSeeecococonnndddarararyyy H H Hoooststst
PPPrrriiimmmarararyyy H H Hoooststst SSSeeecococonnndddarararyyy H H Hoooststst
domains by presenting strength in a system. The PLX SerDes implementation
CPCPCPUUU CPUCPUCPU
CPCPCPUUU CPUCPUCPU
the processor subsystem supports four levels of power off, low, typical, and
as an endpoint rather high. The SerDes block also supports loop-back modes
than another memory and advanced reporting of error conditions, which
RooRooRooRooRooRootttttt
CoCoComplemplemplexxx
CoCoComplemplemplexxx
system. Base address enables efficient management of the entire system.
registers are used to
translate addresses;
Interoperability
NTNT
doorbell registers are The PEX 8632 is designed to be fully compliant with the
PEX 8632PEX 8632PEX 8632PEX 8632
NoNon-Trn-Traansparentnsparent
used to send interrupts PCI Express Base Specification r2.0, and is backwards
PoPorrtt
between the compatible to PCI Express Base Specification r1.1 and
address domains; EnEnEnEnEnEnEnEnd d d d d d d d End End End End End End End End EnEnEnEnEnEnEnEnd d d d d d d d r1.0a. Additionally, it supports auto-negotiation, lane
PoiPoiPoiPoiPoiPoiPoiPoinnnnnnnntttttttt PoiPoiPoiPoiPoiPoiPoiPoinnnnnnnntttttttt PoiPoiPoiPoiPoiPoiPoiPoinnnnnnnntttttttt
and scratchpad reversal, and polarity reversal. Furthermore, the PEX
registers FigureFigure 2. 2. Non Non--TTrraanspansparrenent Port Portt 8632 is designed for Microsoft Vista compliance. All
(accessible from both CPUs) allow inter-processor PLX switches undergo thorough interoperability testing
communication (see Figure 2). in PLXs Interoperability Lab and compliance testing
at the PCI-SIG plug-fest.
Dual Cast
The PEX 8632 supports Dual Cast, a feature which
allows for the copying of data (e.g. packets) from one
ingress port to two egress ports allowing for higher
Applications
performance in dual-graphics, storage, security, and
Suitable for host-centric as well as peer-to-peer traffic
redundant applications.
patterns, the PEX 8632 can be configured for a broad
range of form factors and applications.
Read Pacing
The Read Pacing feature allows users to throttle the
Host Centric Fan-out
amount of read requests being made by downstream
The PEX 8632, with its symmetric or asymmetric lane
devices. When a downstream device requests several
configuration capability, allows user-specific tuning to a
long reads back-to-back, the Root Complex gets tied up
variety of host-centric applications. Figure 3 shows a
in serving this downstream port. If this port has a narrow
typical server-based design where the root complex
link and is therefore slow in receiving these read packets
provides a PCI Express link that needs to be expanded to
from the Root Complex, then other downstream ports
a larger number of smaller ports for a variety of I/O
may become starved thus, impacting performance. The
functions. In this example, the PEX 8632 has an 8-lane
Read Pacing feature enhances performances by allowing
upstream port, and four downstream ports using a
for the adequate servicing of all downstream devices.
combination of x4 and x8 links.
Hot Plug for High Availability
CPCPUU CPCPUU
Hot plug capability allows users to replace hardware
CPCPUU CPCPUU
modules and perform maintenance without powering
down the system. The PEX 8632 hot plug capability
MeMeMeMemmmmoooorrrryyyy
ChChChChipseipseipseipsetttt
feature makes it suitable for High Availability (HA)
applications. Three downstream ports include a
x4 x8
Standard Hot Plug Controller. If the PEX 8632 is used in EndEndEndEndpoipoipoipoinnnntttt
x8
an application where one or more of its downstream
ports connect to PCI Express slots, each ports Hot Plug
PEX 86PEX 863232
PPEX 863EX 86322
Controller can be used to manage the hot-plug event of
x4
x8
its associated slot. Every port on the PEX 8632 is EnEndpoindpointt
EnEndpoindpointt
x8 x4
equipped with a hot-plug control/status register to
Figure 3. Fan-in/out Usage