Version 1.0 2009 PEX 8648 Features Features PE PEXX 8648648 V8 Viittaals ls oo 48-lane, 12-por48-lane, 12-port t PCIe Gen2 switch PCIe Gen2 switch -- IntegratedIntegrated 5.0 5.0 GT/s SerDes GT/s SerDes PCIe Gen2, 5.0GT/s 48-lane, 12-port PCIe Switch 22 oo 27 x 27mm27 x 27mm , 67, 676-pin FCBGA packag6-pin FCBGA package e oo TyTyppiical Power: cal Power: 3.7 Watts 3.7 Watts TM The ExpressLane PEX 8648 device offers PCI Express switching capability enabling users to add scalable high bandwidth, non-blocking PE PEXX 8648648 Key8 Key Fea Feattures ures interconnection to a wide variety of applications including servers, oo StandarStandardds Compliant s Compliant storage systems, and communications platforms. The PEX 8648 is -- PCI Express BasPCI Express Basee Specification, r Specification, r2.0 2.0 (backwards(backwards comcomppatiblatiblee w/ w/ P PCCIe rIe r11.0a/1.0a/1..1)1) well suited for fan-out, aggregation, and peer-to-peer applications. -- PCI Power Management Spec, rPCI Power Management Spec, r1.21.2 -- Microsoft Vista Microsoft Vista Compliant Compliant High Performance & Low Packet Latency -- Supports Access ControlSupports Access Control Servic Serviceess The PEX 8648 architecture supports packet cut-thru with a maximum -- DDyynamic link-width connamic link-width conttrol rol -- DDyynamnamiicc S SeerDesrDes s sppeed eed controcontroll latency of 140ns (x16 to x16). This, combined with large packet memory oo HighHigh P Perforerformamannce ce and non-blocking internal switch architecture, provides full line rate on all -- Non-blocking sNon-blocking swwitch fitch faabric bric ports for performance-hungry applications such as servers and switch -- Full linFull line re raattee on on allall ports ports fabrics. The low latency enables applications to achieve high throughput and -- Packet Cut-ThruPacket Cut-Thru w with 140ns maxith 140ns max pack packet et performance. In addition to low latency, the device supports a packet payload latencylatency (x16 (x16 to to x x16) 16) -- 2KB Max Pay2KB Max Payllooaad Size d Size size of up to 2048 bytes, enabling the user to achieve even higher throughput. -- Read PaRead Pacingcing (ba (bandwidth throndwidth throttlttlining) g) -- Dual-CasDual-Castt Data Integrity oo FlexiblFlexiblee Config Configuration uration The PEX 8648 provides end-to-end CRC (ECRC) protection and Poison bit -- Ports configurabPorts configurable le as x1, x2, x4, as x1, x2, x4, x8, x16x8, x16 -- Registers Registers configconfigurable withurable with strap strappping ing support to enable designs that require end-to-end data integrity. PLX also 22 pins, EEPROM, pins, EEPROM, II C, orC, or host software host software supports data path parity and memory (RAM) error correction as packets -- Lane andLane and polar polarityity reversreversal al pass through the switch. -- ComComppatibleatible with with PCIe 1 PCIe 1..0a PM0a PM oo Dual-Host & Fail-OverDual-Host & Fail-Over Suppor Supportt Flexible Register & Port Configuration -- Configurable NoConfigurable Non-Transparenn-Transparent pt poort rt -- Moveable upstream port Moveable upstream port The PEX 8648s 12 ports can be configured to lane widths of x1, x2, x4, x8, -- Crosslink port Crosslink port capability capability or x16. Flexible buffer allocation, along with the device s flexible packet oo QuQualitality ofy of S Serviervice (ce (QoSQoS) ) flow control, maximizes throughput for applications where more traffic -- Eight traffEight traffiic clasc classes per porses per port t flows in the downstream, rather than upstream, direction. Any port can be -- Weighted rouWeighted round-nd-robin source robin source designated as the upstream port, which can be changed dynamically. The port arbport arbitraitrationtion oo ReliabilitReliability, Avay, Availabilitilability, Sey, Servicrviceabiliteabilityy PEX 8648 also provides -- 3 Hot Plug Ports3 Hot Plug Ports with n with naativtive HP e HP Signals Signals several ways to x4x4 x8x8 22 -- All ports hoAll ports hot pt plluugg cap capablablee thru thru I I C C configure its registers. (Hot Plug Contr(Hot Plug Controollerller on on evereveryy poport) rt) The device can be -- ECRC andECRC and Poison bit support Poison bit support -- Data PaData Path pth paaritrityy configured through PEX 8648PEX 8648PEX 8648 2 PEX 8648PEX 8648PEX 8648 PEPEPEX 8648X 8648X 8648 PPPEX 86EX 86EX 86484848 -- MemoryMemory (RAM) Error (RAM) Error Correctio Correction n strapping pins, I C -- INTA and FATAL ERR signals INTA and FATAL ERR signals interface, host -- Advanced ErrorAdvanced Error Reporting Reporting software, or an optional -- PPoort Srt Sttatusatus b bitsits a and GPnd GPIO avaiIO availablabllee serial EEPROM. This 11 x411 x4 4 x84 x8 2 x42 x4 -- Per port Per port errorerror diagnostics diagnostics -- Performance MoPerformance Monitoringnitoring allows for easy debug Per port pPer port paayyllooaadd & h & headeader er counters counters during the development x8x8 x8x8 phase, performance monitoring during the operation phase, and PEPEPEX 8648X 8648X 8648 PPPEX 8648EX 8648EX 8648 PPPEX 86EX 86EX 86484848 PPPEX 8648EX 8648EX 8648 driver or software upgrade. Figure 1 shows some of the PEX 8648s common port 2 x82 x8 6x46x4 10 x410 x4 configurations. FiguFigure 1. Cre 1. Coommommonn Po Port Cort Connffigurationigurationss Dual-Host & Failover Support ports connect to PCI Express slots, each ports Hot Plug The PEX 8648 product supports a Non-Transparent Controller can be used to manage the hot-plug event of (NT) Port, which enables the implementation of multi- its associated slot. Every port on the PEX 8648 is host systems in communications, storage, and blade equipped with a hot-plug control/status register to server applications. The NT port allows systems to support hot-plug capability through external logic via the 2 isolate host memory domains by presenting the I C interface. processor subsystem as an endpoint rather than another memory system. Base address registers are used to SerDes Power and Signal Management translate addresses doorbell registers are used to send The PEX 8648 supports software control of the SerDes interrupts between the address domains and scratchpad outputs to allow optimization of power and signal registers (accessible by both CPUs) allow inter- strength in a system. The PLX SerDes implementation processor communication (see Figure 2). supports four levels of power off, low, typical, and high. The SerDes block also supports loop-back modes PPPPPPrrrrrriiiiiimmmmmmaaaaaarrrrrry Hy Hy Hy Hoy Hoy Hoooostststststst SSSSSSeeeeeecocococonconconndaryndaryndarydddarararyyy H H H H H Hoooooosssstststttt and advanced reporting of error conditions, which CPUCPUCPUCPUCPUCPU CPUCPUCPUCPUCPUCPU enables efficient management of the entire system. Interoperability Root Root Root Root Root Root ComComComppplexlexlex The PEX 8648 is designed to be fully compliant with the ComComComppplexlexlex PCI Express Base Specification r2.0, and is backwards compatible to PCI Express Base Specification r1.1 and NTNT r1.0a. Additionally, it supports auto-negotiation, lane PEX 8648PEX 8648 PEX 8648PEX 8648 Non-TNon-Trranspansparentarent reversal, and polarity reversal. Furthermore, the PEX PoPortrt 8648 is tested for Microsoft Vista compliance. All PLX switches undergo thorough interoperability testing in EndEndEndEnd End End End End End End End End EndEndEndEnd End End End End End End End End PLXs Interoperability Lab and compliance testing at PoiPoiPoiPoiPoiPoiPoiPoinnnnnnnntttttttt PointPointPointPointPointPointPointPoint PoinPoinPoinPoinPoinPoinPoinPointttttttt the PCI-SIG plug-fest. FFiiggureure 2. 2. Non-Tran Non-Transpsparent Poarent Porrtt Dual Cast The PEX 8648 supports Dual Cast, a feature which Applications allows for the copying of data (e.g. packets) from one ingress port to two egress ports allowing for higher Suitable for host-centric as well as peer-to-peer traffic performance in dual-graphics, storage, security, and patterns, the PEX 8648 can be configured for a wide redundant applications. variety of form factors and applications. Read Pacing Host Centric Fan-out The Read Pacing feature allows users to throttle the The PEX 8648, with its symmetric or asymmetric lane amount of read requests being made by downstream configuration capability, allows user-specific tuning to a devices. When a downstream device requests several variety of host-centric applications. Figure 3 shows a long reads back-to-back, the Root Complex gets tied up typical server design where the root complex provides a in serving this downstream port. If this port has a narrow PCI Express link that needs to be expanded to a larger link and is therefore slow in receiving these read packets number of smaller ports for a variety of I/O functions. In from the Root Complex, then other downstream ports this example, the PEX 8648 has a 16-lane upstream port, may become starved thus, impacting performance. The and five downstream ports using x8 and x4 links. Read Pacing feature enhances performances by allowing for the adequate servicing of all downstream devices. The PEX 8648 can also be used to create PCIe Gen1 (2.5 Gbps) ports. The PEX 8648 is backwards compatible Hot Plug for High Availability with PCIe Gen1 devices. Therefore, the PEX 8648 Hot plug capability allows users to replace hardware enables a Gen 2 native Chip Set to fan-out to Gen 1 modules and perform maintenance without powering endpoints. In Figure 3, the PCIe slots connected to the down the system. The PEX 8648 hot plug capability PEX 8648s downstream ports can be populated with feature makes it suitable for High Availability (HA) either PCIe Gen1 or PCIe Gen 2 devices. Conversely, applications. Three downstream ports include a the PEX 8648 can also be used to create Gen 2 ports on Standard Hot Plug Controller. If the PEX 8648 is used in a Gen 1 native Chip Set in the same fashion. an application where one or more of its downstream