PEX 8664, PCI Express Gen 2 Switch, 64 Lanes, 16 Ports TM Features The ExpressLane PEX 8664 device offers Multi-Host PCI Express PEX 8664 General Features switching capability enabling users to connect multiple hosts to their o 64-lane, 16-port PCIe Gen2 switch respective endpoints via scalable, high bandwidth, non-blocking - Integrated 5.0 GT/s SerDes 2 interconnection to a wide variety of applications including servers, o 35 x 35mm , 1156-ball FCBGA package storage systems, and communications platforms. The PEX 8664 is o Typical Power: 7.9 Watts well suited for fan-out, aggregation, and peer-to-peer applications. PEX 8664 Key Features o Standards Compliant Multi-Host Architecture - PCI Express Base Specification, r2.0 The PEX 8664 employs an enhanced version of PLXs field tested PEX 8648 (backwards compatible w/ PCIe r1.0a/1.1) PCIe switch architecture, which allows users to configure the device in - PCI Power Management Spec, r1.2 legacy single-host mode or multi-host mode with up to five host ports - Microsoft Vista Compliant - Supports Access Control Services capable of 1+1 (one active & one backup) or N+1 (N active & one backup) - Dynamic link-width control host failover. This powerful architectural enhancement enables users to build - Dynamic SerDes speed control PCIe based systems to support high-availability, failover, redundant and o High Performance clustered systems. performancePAK 9 Read Pacing (bandwidth throttling) 9 Multicast High Performance & Low Packet Latency 9 Dynamic Buffer/FC Credit Pool The PEX 8664 architecture supports packet cut-thru with a maximum - Non-blocking switch fabric latency of 176ns (x16 to x16). This, combined with large packet memory, - Full line rate on all ports flexible common buffer/FC credit pool and non-blocking internal switch - Packet Cut-Thru with 176ns max packet latency (x16 to x16) architecture, provides full line rate on all ports for performance-hungry - 2KB Max Payload Size applications such as servers and switch fabrics. The low latency enables o Flexible Configuration applications to achieve high throughput and performance. In addition to low - Ports configurable as x1, x2, x4, x8, x16 latency, the device supports a packet payload size of up to 2048 bytes, - Registers configurable with strapping 2 pins, EEPROM, I C, or host software enabling the user to achieve even higher throughput. - Lane and polarity reversal - Compatible with PCIe 1.0a PM Data Integrity o Multi-Host & Fail-Over Support The PEX 8664 provides end-to-end CRC (ECRC) protection and Poison bit - Configurable Non-Transparent (NT) port support to enable designs that require end-to-end data integrity. PLX also - Failover with NT port - Up to Five upstream/Host ports with 1+1 supports data path parity and memory (RAM) error correction circuitry or N+1 failover to other upstream ports throughout the internal data paths as packets pass through the switch. o Quality of Service (QoS) - Eight traffic classes per port Flexible Configuration - Weighted round-robin source x4 x8 The PEX 8664s 16 ports can be port arbitration o Reliability, Availability, Serviceability configured to lane widths of x1, x2, x4, visionPAK x8, or x16. Flexible buffer allocation, PEXPEX 86 866464 PEXPEX 86 866464 PEPEPEPEX 86X 86X 86X 8664646464 9 Per Port Performance Monitoring along with the device s flexible packet Per port payload & header counters flow control, maximizes throughput 9 SerDes Eye Capture 5 x8 4 x4 15 x4 for applications where more traffic 9 Error Injection and Loopback - 4 Hot Plug Ports with native HP Signals flows in the downstream, rather than 2 x8 x16 - All ports hot plug capable thru I C upstream, direction. Any port can be (Hot Plug Controller on every port) designated as the upstream port, which - ECRC and Poison bit support PEXPEX 86 866464 PEPEX 86X 866464 can be changed dynamically. Figure 1 PEXPEX 86 866464 PEPEX 86X 866464 - Data Path parity - Memory (RAM) Error Correction shows some of the PEX 8664s - INTA and FATAL ERR signals common port configurations in legacy 2 x8 10 x4 6 x8 - Advanced Error Reporting Single-Host mode. Figure 1. Common Port Configurations - Port Status bits and GPIO available - Per port error diagnostics - JTAG AC/DC boundary scan PLX Technology, www.plxtech.com Page 1 of 1 5/14/2009, Version 1.1 PEX 8664, PCI Express Gen 2 Switch, 64 Lanes, 16 Ports The PEX 8664 can also be configured in Multi-Host PEX 8664 allows the hosts to communicate their status mode where users can choose up to five ports as to each other via special door-bell registers. In failover host/upstream ports and assign a desired number of mode, if a host fails, the host designated for failover will downstream ports to each host. In Multi-Host mode, a disable the upstream port attached to the failing host and virtual switch is created for each host port and its program the downstream ports of that host to its own associated downstream ports inside the device. The domain. Figure 4a shows a two host system in Multi- traffic between the ports of a virtual switch is completely Host mode with two virtual switches inside the device isolated from the traffic in other virtual switches. Figure and Figure 4b shows Host 1 disabled after failure and 2 illustrates some configurations of the PEX 8664 in Host 2 having taken over all of Host 1s end-points. Multi-Host mode where each ellipse represents a virtual HoHost 1st 1 HoHosstt 2 2 HostHost 1 1 HoHostst 2 2 HoHost 1st 1 HoHosstt 2 2 HostHost 1 1 HoHostst 2 2 switch inside the device. x8 x8 x8 x4 x4 PEX 8664 PEX 8664 PEX 8664 PEX 8664 The PEX 8664 also provides several ways to PPPEPEEX 86EX 86X 86X 8664646464 PEPEPPEEX 8X 8XX 86 866666646444 EnEnEnEnd d d d EnEnEnEnd d d d EndEndEndEnd EnEnEnEnd d d d EndEndEndEnd EnEnEnEnd d d d EnEnEnEnd d d d EndEndEndEnd configure its registers. The PoPoPoPointintintint PoinPoinPoinPointttt PoPoPoPointintintint PoPoPoPointintintint PoPoPoPoiiiinnnntttt PoPoPoPointintintint PoinPoinPoinPointttt PoinPoinPoinPointttt Figure 4a. Multi-Host Figure 4b. Multi-Host Fail-Over device can be configured x8x8x4x4 x8x8x4x4 3 x8 3 x4 3 x4 through strapping pins, 4 x4s4 x4s 5 x4s5 x4s 2 I C interface, host Hot Plug for High Availability software, or an optional Hot plug capability allows users to replace hardware PPPPPPEX 86EX 86EX 86EX 86EX 86EX 86646464646464 PEPEPEX 86X 86X 86646464 PEPEPEX 8X 8X 8666666444 serial EEPROM. This modules and perform maintenance without powering allows for easy debug down the system. The PEX 8664 hot plug capability 12 x4s12 x4s 11 x411 x4ss during the development feature makes it suitable for High Availability (HA) Figure 2. Common Multi-Host Configurations phase, performance applications. Four downstream ports include a Standard monitoring during the operation phase, and driver or Hot Plug Controller. If the PEX 8664 is used in an software upgrade. application where one or more of its downstream ports connect to PCI Express slots, each ports Hot Plug Dual-Host & Failover Support Controller can be used to manage the hot-plug event of In Single-Host mode, the its associated slot. Every port on the PEX 8664 is PPPrrrimimimararary Hy Hy Hoooststst SSSecoecoecondndndary Hary Hary Hoooststst PEX 8664 supports a Non- PPPrrriiimmmaaarrry Hy Hy Hoooststst SSSecoecoecondndndary Hary Hary Hoooststst equipped with a hot-plug control/status register to CPUCPUCPU CPUCPUCPU CPUCPUCPU CPUCPUCPU Transparent (NT) Port, support hot-plug capability through external logic via the 2 which enables the I C interface. Root Root Root Root Root Root implementation of dual- host ComplexComplexComplex ComplexComplexComplex systems for redundancy and host SerDes Power and Signal Management failover capability. The NT port The PEX 8664 supports software control of the SerDes NTNT allows systems to isolate outputs to allow optimization of power and signal PEX 8664PEX 8664 PEX 8664PEX 8664 NNoonn--TranTranspsparenarentt host memory domains by strength in a system. The PLX SerDes implementation PorPortt presenting the supports four levels of power off, low, typical, and EnEnEnEnEnEnEnEnd d d d d d d d EEEEEEEEnd nd nd nd nd nd nd nd EEEEEEEEnd nd nd nd nd nd nd nd processor subsystem as an high. The SerDes block also supports loop-back modes PoPoPoPoinininintttt PoPoPoPoinininintttt PoPoPoPoiiiinnnntttt PoPoPoPoinininintttt PoPoPoPoinininintttt PoPoPoPoiiiinnnntttt endpoint rather than and advanced reporting of error conditions, which FiguFigurere 3. 3. Non Non--TranspareTransparennt Port Portt another memory enables efficient management of the entire system. system. Base address registers are used to translate addresses doorbell registers are used to send interrupts Interoperability between the address domains and scratchpad registers The PEX 8664 is designed to be fully compliant with the (accessible by both CPUs) allow inter-processor PCI Express Base Specification r2.0, and is backwards communication (Figure 3). compatible to PCI Express Base Specification r1.1 and r1.0a. Additionally, it supports auto-negotiation, lane Multi-Host & Failover Support reversal, and polarity reversal. Furthermore, the PEX In Multi-Host mode, PEX 8664 can be configured with 8664 is tested for Microsoft Vista compliance. All PLX up to five upstream host ports, each with its own switches undergo thorough interoperability testing in dedicated downstream ports. The device can be PLXs Interoperability Lab and compliance testing at configured for 1+1 redundancy or N+1 redundancy. The the PCI-SIG plug-fest. PLX Technology, www.plxtech.com Page 2 of 2 5/14/2009, Version 1.1