PEX 8680, PCI Express Gen 2 Switch, 80 Lanes, 20 Ports TM Features The ExpressLane PEX 8680 device offers Multi-Host PCI Express PEX 8680 General Features switching capability enabling users to connect multiple hosts to their o 80-lane, 20-port PCIe Gen2 switch respective endpoints via scalable, high bandwidth, non-blocking - Integrated 5.0 GT/s SerDes 2 interconnection to a wide variety of applications including servers, o 35 x 35mm , 1156-ball FCBGA package storage systems, and communications platforms. The PEX 8680 is o Typical Power: 9.0 Watts well suited for fan-out, aggregation, and peer-to-peer applications. PEX 8680 Key Features o Standards Compliant Multi-Host Architecture - PCI Express Base Specification, r2.0 The PEX 8680 employs an enhanced version of PLXs field tested PEX 8648 (backwards compatible w/ PCIe r1.0a/1.1) PCIe switch architecture, which allows users to configure the device in - PCI Power Management Spec, r1.2 legacy single-host mode or multi-host mode with up to six host ports capable - Microsoft Vista Compliant - Supports Access Control Services of 1+1 (one active & one backup) or N+1 (N active & one backup) host - Dynamic link-width control failover. This powerful architectural enhancement enables users to build - Dynamic SerDes speed control PCIe based systems to support high-availability, failover, redundant and o High Performance clustered systems. performancePAK 9 Read Pacing (bandwidth throttling) 9 Multicast High Performance & Low Packet Latency 9 Dynamic Buffer/FC Credit Pool The PEX 8680 architecture supports packet cut-thru with a maximum - Non-blocking switch fabric latency of 176ns (x16 to x16). This, combined with large packet memory, - Full line rate on all ports flexible common buffer/FC credit pool and non-blocking internal switch - Packet Cut-Thru with 176ns max packet latency (x16 to x16) architecture, provides full line rate on all ports for performance-hungry - 2KB Max Payload Size applications such as servers and switch fabrics. The low latency enables o Flexible Configuration applications to achieve high throughput and performance. In addition to low - Ports configurable as x1, x2, x4, x8, x16 latency, the device supports a packet payload size of up to 2048 bytes, - Registers configurable with strapping 2 pins, EEPROM, I C, or host software enabling the user to achieve even higher throughput. - Lane and polarity reversal - Compatible with PCIe 1.0a PM Data Integrity o Multi-Host & Fail-Over Support The PEX 8680 provides end-to-end CRC (ECRC) protection and Poison bit - Configurable Non-Transparent (NT) port support to enable designs that require end-to-end data integrity. PLX also - Failover with NT port - Up to Six upstream/Host ports with 1+1 supports data path parity and memory (RAM) error correction circuitry or N+1 failover to other upstream ports throughout the internal data paths as packets pass through the switch. o Quality of Service (QoS) - Eight traffic classes per port Flexible Configuration - Weighted round-robin source The PEX 8680s 20 ports can be configured to lane widths of x1, x2, x4, x8, port arbitration o Reliability, Availability, Serviceability or x16. Flexible buffer x4 x8 visionPAK allocation, along with the 9 Per Port Performance Monitoring device s flexible packet Per port payload & header counters flow control, maximizes 9 SerDes Eye Capture PEX 8680PEX 8680PEX 8680PEX 8680 PEX 8680PEX 8680PEX 8680PEX 8680 throughput for applications 9 Error Injection and Loopback - 4 Hot Plug Ports with native HP Signals where more traffic flows in 2 - All ports hot plug capable thru I C the downstream, rather than (Hot Plug Controller on every port) 19 x4 6 x8 6 x4 upstream, direction. Any - ECRC and Poison bit support port can be designated as the - Data Path parity x16 x8 - Memory (RAM) Error Correction upstream port, which can be - INTA and FATAL ERR signals changed dynamically. - Advanced Error Reporting Figure 1 shows some of the - Port Status bits and GPIO available PEX 8680PEX 8680PEX 8680PEX 8680 PEX 8680PEX 8680PEX 8680PEX 8680 PEX 8680s common port - Per port error diagnostics configurations in legacy - JTAG AC/DC boundary scan Single-Host mode. 4 x8 10 x4 8 x8 Figure 1. Common Port Configurations PLX Technology, www.plxtech.com Page 1 of 1 5/14/2009, Version 1.1 PEX 8680, PCI Express Gen 2 Switch, 80 Lanes, 20 Ports The PEX 8680 can also be configured in Multi-Host Multi-Host & Failover Support mode where users can choose up to six ports as In Multi-Host mode, PEX 8680 can be configured with host/upstream ports and assign a desired number of up to six upstream host ports, each with its own downstream ports to each host. In Multi-Host mode, a dedicated downstream ports. The device can be virtual switch is created for each host port and its configured for 1+1 redundancy or N+1 redundancy. The associated downstream ports inside the device. The PEX 8680 allows the hosts to communicate their status traffic between the ports of a virtual switch is completely to each other via special door-bell registers. In failover isolated from the traffic in other virtual switches. Figure mode, if a host fails, the host designated for failover will 2 illustrates some configurations of the PEX 8680 in disable the upstream port attached to the failing host and Multi-Host mode where each ellipse represents a virtual program the downstream ports of that host to its own switch inside the device. domain. Figure 4a shows a two host system in Multi- Host mode with two virtual switches inside the device The PEX 8680 x8 x8 x8 x8 x8 and Figure 4b shows Host 1 disabled after failure and also provides Host 2 having taken over all of Host 1s end-points. several ways to HostHost 1 1 HostHost 2 2 HoHost 1st 1 HoHost 2st 2 HostHost 1 1 HostHost 2 2 HoHost 1st 1 HoHost 2st 2 configure its PEX 8680PEX 8680 PEX 8680PEX 8680 PEX 8680PEX 8680 PEX 86PEX 868080 registers. The PEX 8680PEX 8680 PEX 8680PEX 8680 device can be configured 2 x8, 4 x4 2 x8, 4x4 4 x4 4 x4 4 x4 EnEnd d EnEnd d EnEnd d EnEnd d EndEnd EEnd nd EndEnd EnEnd d EnEnd d EnEnd d EnEnd d EnEnd d EndEnd EEnd nd EndEnd EnEnd d through 4 x4s 6 x4s PoPoPoPoinininintttt PoinPoinPoinPointttt PoPoPoPointintintint PoPoPoPoiiiintntntnt PoPoPoPoiiiintntntnt PoPoPoPointintintint PoPoPoPoinininintttt PoinPoinPoinPointttt Figure 4a. Multi-Host Figure 4b. Multi-Host Fail-Over strapping pins, 2 I C interface, host software, or Hot Plug for High Availability PEX 8680PEX 8680PPEX 868EX 86800 PEX 8680PEX 8680 PEX 8680PEX 8680 an optional Hot plug capability allows users to replace hardware serial modules and perform maintenance without powering EEPROM. down the system. The PEX 8680 hot plug capability 16 x4s 12 x4s Figure 2. Common Multi-Host Configurations This allows feature makes it suitable for High Availability (HA) for easy debug during the development phase, applications. Four downstream ports include a Standard performance monitoring during the operation phase, and Hot Plug Controller. If the PEX 8680 is used in an driver or software upgrade. application where one or more of its downstream ports connect to PCI Express slots, each ports Hot Plug Dual-Host & Failover Support Controller can be used to manage the hot-plug event of In Single-Host mode, the PEX 8680 supports a Non- its associated slot. Every port on the PEX 8680 is Transparent (NT) Port, which enables the equipped with a hot-plug control/status register to implementation of dual-host systems for redundancy support hot-plug capability through external logic via the 2 and host failover capability. I C interface. PPPPPPrrrrrriiiiiimmmmmmarararararary Hy Hy Hy Hy Hy Hoooooostststststst SSSSSSeeeeeecondary Hcondary Hcondary Hcondary Hcondary Hcondary Hoooooosssssstttttt The NT port allows systems CPCPCPCPCPCPUUUUUU CPUCPUCPUCPUCPUCPU to isolate host memory SerDes Power and Signal Management domains by presenting the The PEX 8680 supports software control of the SerDes RootRootRoot RootRootRoot CompleCompleComplexxx CompleCompleComplexxx processor subsystem as an outputs to allow optimization of power and signal endpoint rather than strength in a system. The PLX SerDes implementation another memory system. NTNT Base supports four levels of power off, low, typical, and PEX 8680PEX 8680 PEX 86PEX 868080 address registers are used high. The SerDes block also supports loop-back modes Non-Non-TrTransanspparearenntt PoPorrtt to translate addresses and advanced reporting of error conditions, which doorbell registers are EndEndEndEndEndEndEndEnd EnEnEnEnEnEnEnEndddddddd EndEndEndEndEndEndEndEnd enables efficient management of the entire system. PointPointPointPointPointPointPointPoint PoPoPoPoPoPoPoPoinininininininintttttttt PointPointPointPointPointPointPointPoint used to send FFiigugurere 3. 3. NonNon--TTrranspansparearennt Pot Porrtt interrupts between the Interoperability address domains and scratchpad registers (accessible by The PEX 8680 is designed to be fully compliant with the both CPUs) allow inter-processor communication (see PCI Express Base Specification r2.0, and is backwards Figure 3). compatible to PCI Express Base Specification r1.1 and PLX Technology, www.plxtech.com Page 2 of 2 5/14/2009, Version 1.1