PEX8714, PCI Express Gen3 Switch, 12 Lanes, 5 Ports TM Highlights The ExpressLane PEX8714 device offers Multi-Host PCI Express switching capability enabling users to connect multiple hosts to their PEX8714 General Features respective endpoints via scalable, high bandwidth, non-blocking o 12-lane, 5-port PCIe Gen3 switch Integrated 8.0 GT/s SerDes interconnection to a wide variety of applications including servers, storage 2 o 19 x 19mm , 324-ball FCBGA package systems, and communications platforms. The PEX8714 is well suited for o Typical Power: 2.7 Watts fan-out, aggregation, and peer-to-peer applications. PEX8714 Key Features Multi-Host Architecture o Standards Compliant The PEX8714 employs an enhanced architecture, which allows users to PCI Express Base Specification, r3.0 (compatible w/ PCIe r1.0a/1.1 & 2.0) configure the device in legacy single-host mode or multi-host mode with up PCI Power Management Spec, r1.2 to two host ports by using NT capability. This powerful architectural Microsoft Windows Logo Compliant enhancement enables users to build PCIe based systems to support high- Supports Access Control Services availability, failover, redundant and clustered systems. Dynamic link-width control Dynamic SerDes speed control High Performance & Low Packet Latency o High Performance The PEX8714 architecture supports packet cut-thru with a maximum performancePAK latency of 158ns (x4 to x4). This, combined with large packet memory, Multicast Dynamic Buffer/FC Credit Pool flexible common buffer/FC credit pool and non-blocking internal switch Non-blocking switch fabric architecture, provides full line rate on all ports for performance-hungry Full line rate on all ports applications such as servers and switch fabrics. The low latency enables Cut-Thru with 154ns max packet latency applications to achieve high throughput and performance. In addition to low 2KB Max Payload Size o Multi-Host & Fail-Over Support latency, the device supports a packet payload size of up to 2048 bytes, 1 Configurable Non-Transparent ports enabling the user to achieve even higher throughput. Failover with Non-Transparent port o Quality of Service (QoS) Data Integrity Traffic Class Queuing The PEX8714 provides end-to-end CRC (ECRC) protection and Poison bit Eight traffic classes per port support to enable designs that require end-to-end data integrity. PLX also Weighted round-robin source supports data path parity and memory (RAM) error correction circuitry port arbitration o Reliability, Availability, Serviceability throughout the internal data paths as packets pass through the switch. visionPAK Flexible Configuration Per Port Performance Monitoring SerDes Eye Capture The PEX8714s 5 ports can be configured PCIe Packet Generator to lane widths of x2, x4, or x8. Flexible Error Injection and Loopback buffer allocation, along with the device s 1 Hot-Plug port with native HP Signals 2 flexible packet flow control, maximizes All ports Hot-Plug capable thru I C throughput for applications where more SSC Isolation on up to 4 ports ECRC and Poison bit support traffic flows in the downstream, rather Data Path parity than upstream, direction. Any port can be Memory (RAM) Error Correction designated as the upstream port, which Advanced Error Reporting can be changed dynamically. Figure 1 Port Status bits and GPIO available JTAG AC/DC boundary scan shows some of the PEX8714s common port configurations in legacy Single-Host mode. PLX Technology, www.plxtech.com Page 1 of 4 10Sep12 v1.0 PEX8714, PCI Express Gen3 Switch, 12 Lanes, 5 Ports The PEX8714 also provides several ways to configure and advanced reporting of error conditions, which its registers. The device can be configured through enables efficient management of the entire system. 2 strapping pins, I C interface, host software, or an optional serial EEPROM. This allows for easy debug Interoperability during the development phase, performance monitoring The PEX8714 is designed to be fully compliant with the during the operation phase, and driver or software PCI Express Base Specification r3.0, and is backwards upgrade. compatible to PCI Express Base Specification r1.1 and r1.0a. Additionally, it supports auto-negotiation, lane Dual-Host & Failover Support reversal, and polarity reversal. Furthermore, the In Single-Host mode, the PEX8714 supports a Non- PEX8714 is tested for Microsoft Windows Logo Transparent (NT) Port, which enables the compliance. All PLX switches undergo thorough implementation of dual-host systems for redundancy interoperability testing in PLXs Interoperability Lab and host failover and compliance testing at the PCI-SIG plug-fest. capability. The NT port allows systems to isolate host memory domains by presenting the processor subsystem as an endpoint rather than another memory system. Base address registers are used to translate addresses doorbell registers are used to send interrupts between the address domains and scratchpad registers (accessible by both CPUs) allow inter- processor communication (see Figure 3). Hot-Plug for High Availability Hot plug capability allows users to replace hardware modules and perform maintenance without powering down the system. The PEX8714 Hot-Plug capability feature makes it suitable for High Availability (HA) applications. One downstream ports include a Standard Hot Plug Controller. If the PEX8714 is used in an application where one or more of its downstream ports connect to PCI Express slots, each ports Hot-Plug Controller can be used to manage the Hot-Plug event of its associated slot. Every port on the PEX8714 is equipped with a Hot-Plug control/status register to support Hot-Plug capability through external logic via 2 the I C interface. SerDes Power and Signal Management The PEX8714 supports software control of the SerDes outputs to allow optimization of power and signal strength in a system. The PLX SerDes implementation supports four levels of power off, low, typical, and high. The SerDes block also supports loop-back modes PLX Technology, www.plxtech.com Page 2 of 4 10Sep12 v1.0