PEX8734, PCI Express Gen3 Switch, 32 Lanes, 8 Ports TM Highlights The ExpressLane PEX8734 device offers Multi-Host PCI Express switching capability enabling users to connect multiple hosts to their PEX8734 General Features respective endpoints via scalable, high bandwidth, non-blocking o 32-lane, 8-port PCIe Gen3 switch Integrated 8.0 GT/s SerDes interconnection to a wide variety of applications including servers, storage 2 o 27 x 27mm , 676-ball FCBGA package systems, and communications platforms. The PEX8734 is well suited for o Typical Power: 6.2 Watts fan-out, aggregation, and peer-to-peer applications. PEX8734 Key Features Multi-Host Architecture o Standards Compliant The PEX8734 employs an enhanced architecture, which allows users to PCI Express Base Specification, r3.0 (compatible w/ PCIe r1.0a/1.1 & 2.0) configure the device in legacy single-host mode or multi-host mode with up PCI Power Management Spec, r1.2 to three host ports capable of 1+1 (one active & one backup) or N+1 (N Microsoft Windows Logo Compliant active & one backup) host failover. This powerful architectural enhancement Supports Access Control Services enables users to build PCIe based systems to support high-availability, Dynamic link-width control failover, redundant and clustered systems. Dynamic SerDes speed control o High Performance High Performance & Low Packet Latency performancePAK The PEX8734 architecture supports packet cut-thru with a maximum Multicast Dynamic Buffer/FC Credit Pool latency of 150ns (x16 to x16). This, combined with large packet memory, Non-blocking switch fabric flexible common buffer/FC credit pool and non-blocking internal switch Full line rate on all ports architecture, provides full line rate on all ports for performance-hungry Cut-Thru with 150ns max packet latency applications such as servers and switch fabrics. The low latency enables 2KB Max Payload Size o Multi-Host & Fail-Over Support applications to achieve high throughput and performance. In addition to low 2 Configurable Non-Transparent ports latency, the device supports a packet payload size of up to 2048 bytes, Failover with Non-Transparent port enabling the user to achieve even higher throughput. Up to 2 upstream/Host ports with 1+1 or N+1 failover to other upstream ports Data Integrity o Quality of Service (QoS) The PEX8734 provides end-to-end CRC (ECRC) protection and Poison bit Traffic Class Queuing support to enable designs that require end-to-end data integrity. PLX also Eight traffic classes per port Weighted round-robin source supports data path parity and memory (RAM) error correction circuitry port arbitration throughout the internal data paths as packets pass through the switch. o Reliability, Availability, Serviceability visionPAK Flexible Configuration Per Port Performance Monitoring The PEX8734s 8 ports can be configured to SerDes Eye Capture lane widths of x4, x8, or x16. Flexible PCIe Packet Generator buffer allocation, along with the device s Error Injection and Loopback flexible packet flow control, maximizes 2 Hot-Plug port with native HP Signals 2 All ports Hot-Plug capable thru I C throughput for applications where more SSC Isolation on up to 8 ports traffic flows in the downstream, rather than ECRC and Poison bit support upstream, direction. Any port can be Data Path parity designated as the upstream port, which can Memory (RAM) Error Correction Advanced Error Reporting be changed dynamically. Figure 1 shows Port Status bits and GPIO available some of the JTAG AC/DC boundary scan PEX8734s common port configurations in legacy Single-Host mode. The PEX8734 can also be configured in Multi-Host mode where users can choose up to two ports as host/upstream ports and assign a desired number of downstream ports to each host. In Multi-Host mode, a virtual switch is created for each host port and its associated downstream ports inside the device. The traffic between the ports of a virtual switch is completely isolated from the traffic in other virtual switches. Figure 2 illustrates some configurations of the PEX8734 in Multi-Host mode where each ellipse represents a virtual switch inside the device. PLX Technology, www.plxtech.com Page 1 of 5 10Sep12 v1.0 PEX8734, PCI Express Gen3 Switch, 32 Lanes, 8 Ports The PEX8734 also provides several ways to configure Hot-Plug for High Availability its registers. The device can be configured through Hot plug capability allows users to replace hardware 2 strapping pins, I C interface, host software, or an modules and perform maintenance without powering optional serial EEPROM. This allows for easy debug down the system. The PEX8734 Hot-Plug capability during the development phase, performance monitoring feature makes it suitable for High Availability (HA) during the operation phase, and driver or software applications. Two downstream ports include a Standard upgrade. Hot Plug Controller. If the PEX8734 is used in an application where one or more of its downstream ports Dual-Host & Failover Support connect to PCI Express slots, each ports Hot-Plug In Single-Host mode, the PEX8734 supports a Non- Controller can be used to manage the Hot-Plug event of Transparent (NT) Port, which enables the its associated slot. Every port on the PEX8734 is implementation of dual-host systems for redundancy equipped with a Hot-Plug control/status register to and host failover support Hot-Plug capability through external logic via 2 capability. The NT the I C interface. port allows systems to isolate host SerDes Power and Signal Management memory domains by The PEX8734 supports software control of the SerDes presenting the outputs to allow optimization of power and signal processor subsystem strength in a system. The PLX SerDes implementation as an endpoint rather supports four levels of power off, low, typical, and than another memory high. The SerDes block also supports loop-back modes system. Base address and advanced reporting of error conditions, which registers are used to enables efficient management of the entire system. translate addresses doorbell registers are used to send interrupts between the address domains and scratchpad Interoperability registers (accessible by both CPUs) allow inter- The PEX8734 is designed to be fully compliant with the processor communication (see Figure 3). PCI Express Base Specification r3.0, and is backwards compatible to PCI Express Base Specification r1.1 and Multi-Host & Failover Support r1.0a. Additionally, it supports auto-negotiation, lane In Multi-Host mode, PEX8734 can be configured with reversal, and polarity reversal. Furthermore, the up to two upstream host ports, each with its own PEX8734 is tested for Microsoft Windows Logo dedicated downstream ports. The device can be compliance. All PLX switches undergo thorough configured for 1+1 redundancy or N+1 redundancy. The interoperability testing in PLXs Interoperability Lab PEX8734 allows the hosts to communicate their status to and compliance testing at the PCI-SIG plug-fest. each other via special door-bell registers. In failover mode, if a host fails, the host designated for failover will disable the upstream port attached to the failing host and program the downstream ports of that host to its own domain. Figure 4a shows a two host system in Multi- Host mode with two virtual switches inside the device and Figure 4b shows Host 1 disabled after failure and Host 2 having taken over all of Host 1s end-points. PLX Technology, www.plxtech.com Page 2 of 5 10Sep12 v1.0