PEX 8748, PCI Express Gen 3 Switch, 48 Lanes, 12 Ports Highlights The ExpressLane PEX 8748 device offers Multi-Host PCI Express switching capability enabling users to connect multiple hosts to their PEX 8748 General Features o 48-lane, 12-port PCIe Gen 3 switch respective endpoints via scalable, high bandwidth, non-blocking - Integrated 8.0 GT/s SerDes 2 interconnection to a wide variety of applications including servers, o 27 x 27mm , 676-pin FCBGA package o Typical Power: 8.0 Watts storage, communications, and graphics platforms. The PEX 8748 is well suited for fan-out, aggregation, and peer-to-peer traffic patterns. PEX 8748 Key Features o Standards Compliant Multi-Host Architecture - PCI Express Base Specification, r3.0 The PEX 8748 employs an enhanced version of PLXs field tested PEX 8648 (compatible w/ PCIe r1.0a/1.1 & 2.0) PCIe switch architecture, which allows users to configure the device in legacy - PCI Power Management Spec, r1.2 - Microsoft Vista Compliant single-host mode or multi-host mode with up to six host ports capable of 1+1 - Supports Access Control Services (one active & one backup) or N+1 (N active & one backup) host failover. This - Dynamic link-width control powerful architectural enhancement enables users to build PCIe based systems - Dynamic SerDes speed control to support high-availability, failover, redundant, or clustered systems. o High Performance performancePAK 9 Read Pacing (bandwidth throttling) High Performance & Low Packet Latency 9 Multicast The PEX 8748 architecture supports packet cut-thru with a maximum 9 Dynamic Buffer/FC Credit Pool latency of 100ns (x16 to x16). This, combined with large packet memory, - Non-blocking switch fabric flexible common buffer/FC credit pool and non-blocking internal switch - Full line rate on all ports - Packet Cut-Thru with 100ns max packet architecture, provides full line rate on all ports for performance-hungry latency (x16 to x16) applications such as servers and switch fabrics. The low latency enables - 2KB Max Payload Size applications to achieve high throughput and performance. In addition to low o Flexible Configuration latency, the device supports a packet payload size of up to 2048 bytes, - Ports configurable as x1, x2, x4, x8, x16 enabling the user to achieve even higher throughput. - Registers configurable with strapping 2 pins, EEPROM, I C, or host software - Lane and polarity reversal Data Integrity - Compatible with PCIe 1.0a PM The PEX 8748 provides end-to-end CRC (ECRC) protection and Poison bit o Multi-Host & Fail-Over Support support to enable designs that require end-to-end data integrity. PLX also - Configurable Non-Transparent (NT) port - Failover with NT port supports data path parity and memory (RAM) error correction circuitry - Up to 6 upstream/Host ports with 1+1 or throughout the internal data paths as packets pass through the switch. N+1 failover to other upstream ports o Quality of Service (QoS) Flexible Configuration - Eight traffic classes per port The PEX 8748s 12 ports can be - Weighted round-robin source x4x4 x8x8 port arbitration configured to lane widths of x1, o Reliability, Availability, Serviceability x2, x4, x8, or x16. Flexible buffer visionPAK allocation, along with the device s PEX 8748PEX 8748PEX 8748 9 Per Port Performance Monitoring PPPEEEX 87X 87X 87484848 PEX 8748PEX 8748PEX 8748PPPEEEX 87X 87X 87484848 flexible packet flow control, Per port payload & header counters maximizes throughput for 9 SerDes Eye Capture 9 PCIe Packet Generator applications where more traffic 1111 x4 x4 4 x4 x88 2 x42 x4 9 Error Injection and Loopback flows in the downstream, rather - 3 Hot Plug Ports with native HP Signals x8x8 than upstream, direction. Any x8x8 2 - All ports hot plug capable thru I C port can be designated as the (Hot Plug Controller on every port) upstream port, which can be - ECRC and Poison bit support PEX 8748PEX 8748PEX 8748 PEX 8748PEX 8748PEX 8748PPPEEEX 87X 87X 87484848 PPPEEEX 87X 87X 87484848 - Data Path parity changed dynamically. Figure 1 - Memory (RAM) Error Correction shows some of the PEX 8748s - INTA and FATAL ERR signals common port configurations in - Advanced Error Reporting 2 x82 x8 6x6x44 1010 x4 x4 legacy Single-Host mode. - Port Status bits and GPIO available FFiigugure re 1. Commo1. Common Porn Portt CConfonfiguiguratiorationsns Per port error diagnostics - JTAG AC/DC boundary scan PLX Technology, www.plxtech.com Page 1 of 5 10/20/2010, Version 1.0 PEX 8748, PCI Express Gen 3 Switch, 48 Lanes, 12 Ports The PEX 8748 can also be configured in Multi-Host mode Multi-Host & Failover Support where users can choose up to six ports as host/upstream In Multi-Host mode, PEX 8748 can be configured with up ports and assign a desired number of downstream ports to to six upstream host ports, each with its own dedicated each host. In Multi-Host mode, a virtual switch is created downstream ports. The device can be configured for 1+1 for each host port and its associated downstream ports redundancy or N+1 redundancy. The PEX 8748 allows the inside the device. The traffic between the ports of a virtual hosts to communicate their status to each other via special switch is completely isolated from the traffic in other door-bell registers. In failover mode, if a host fails, the virtual switches. Figure 2 illustrates some configurations host designated for failover will disable the upstream port of the PEX 8748 in Multi-Host mode where each ellipse attached to the failing host and program the downstream represents a virtual switch inside the device. ports of that host to its own domain. Figure 4a shows a two host system in Multi-Host mode with two virtual switches x8 x8 x8 x4 x4 The PEX 8748 inside the device and Figure 4b shows Host 1 disabled also provides after failure and Host 2 having taken over all of Host 1s several ways to end-points. configure its PEX 8748PEX 8748PEX 87PEX 874848 PEXPEXPEX 8748PEX 8748 8748 8748 HosHost 1t 1 HosHost 2t 2 HosHostt 1 1 HosHostt 2 2 HosHost 1t 1 HosHost 2t 2 HosHostt 1 1 HosHostt 2 2 registers. The device can be PEX 8748 PEX 8748 PEX 8748 PEX 8748 configured 4 x4 4 x4 2 x4 3 x4 3 x4 through strapping 3 x4s 4 x4s 2 pins, I C EnEnd d EnEnd d EEnd nd EEnd nd EnEnd d EnEnd d EnEnd d EnEnd d EnEnd d EnEnd d EEnd nd EEnd nd EnEnd d EnEnd d EnEnd d EnEnd d interface, host PoPoPoPointintintint PoPoPoPointintintint PoPoPoPointintintint PoPoPoPointintintint PoPoPoPoiiiinnnntttt PoPoPoPoiiiinnnntttt PoPoPoPoinininintttt PoPoPoPointintintint software, or an Figure 4a. Multi-Host Figure 4b. Multi-Host Fail-Over PEX 8748PEX 8748 PEX 8748PEX 8748 PEX 87PEX 87PEX 8748PEX 87484848 optional serial Hot Plug for High Availability EEPROM. This Hot plug capability allows users to replace hardware allows for easy 9 x4s 8 x4s modules and perform maintenance without powering down debug during the Figure 2. Multi-Host Port Configurations the system. The PEX 8748 hot plug capability feature development makes it suitable for High Availability (HA) phase, performance monitoring during the operation phase, applications. Three downstream ports include a Standard and driver or software upgrade. Hot Plug Controller. If the PEX 8748 is used in an application where one or more of its downstream ports Dual-Host & Failover Support connect to PCI Express slots, each ports Hot Plug In Single-Host mode, the PEX 8748 supports a Non- Controller can be used to manage the hot-plug event of its Transparent (NT) Port, which enables the associated slot. Every port on the PEX 8748 is equipped implementation of with a hot-plug control/status register to support hot-plug PPPrrriiimmmary Hary Hary Hoooststst SSSeeecondacondacondarrryyy H H Hoooststst PPPrrriiimmmararary Hoy Hoy Hosssttt SSSecoecoeconnndddary Hary Hary Hoooststst dual-host systems for 2 CPCPCPCPCPCPUUUUUU CPUCPUCPUCPUCPUCPU capability through external logic via the I C interface. redundancy and host failover capability. The SerDes Power and Signal Management NT port allows systems Root Root Root Root Root Root CoCoCoCoCoComplmplmplmplmplmpleeeeeexxxxxx The PEX 8748 provides low power capability that is fully to isolate host memory compliant with the PCIe power management specification domains by presenting and supports software control of the SerDes outputs to NTNT the processor subsystem allow optimization of power and signal strength in a PEX 8748PEX 8748 as an endpoint rather than PEPEX 8748X 8748 NoNon-n-TranspaTransparrentent PorPortt system. Furthermore, the SerDes block supports loop-back another memory modes and advanced reporting of error conditions, system. Base address EndEndEndEnd End End End End End End End End EndEndEndEnd End End End End End End End End PointPointPointPointPointPointPointPoint PointPointPointPointPointPointPointPoint PointPointPointPointPointPointPointPoint which enables efficient management of the entire system. registers are used to FigurFiguree 3. 3. N Noonn-T-Trranspansparenarent Pt Poorrtt translate addresses Interoperability doorbell registers are used to send interrupts between the The PEX 8748 is designed to be fully compliant with the address domains and scratchpad registers (accessible by PCI Express Base Specification r2.0, and is backwards both CPUs) allow inter-processor communication (see compatible to PCI Express Base Specification r1.1 and Figure 3). PLX Technology, www.plxtech.com Page 2 of 5 10/20/2010, Version 1.0