CDM4-600LR
SURFACE MOUNT SILICON
www.centralsemi.com
N-CHANNEL
DESCRIPTION:
LR POWER MOSFET
The CENTRAL SEMICONDUCTOR CDM4-600LR is a
4.0 AMP, 600 VOLT
600 Volt N-Channel MOSFET designed for high voltage,
fast switching applications such as Power Factor
Correction (PFC), lighting and power inverters. This
TM
UltraMOS MOSFET combines high voltage capability
with ultra low r , low threshold voltage, and low
DS(ON)
gate charge for optimal efficiency.
MARKING: FULL PART NUMBER
DPAK CASE
APPLICATIONS: FEATURES:
Power Factor Correction High voltage capability (V =600V)
DS
Alternative energy inverters Low gate charge (Q =2.04nC TYP)
gs
Solid State Lighting (SSL) Ultra low r (0.65 TYP)
DS(ON)
MAXIMUM RATINGS: (T =25C unless otherwise noted)
C
SYMBOL UNITS
Drain-Source Voltage V 600 V
DS
Gate-Source Voltage V 30 V
GS
Continuous Drain Current (Steady State) I 4.0 A
D
Maximum Pulsed Drain Current, tp=10s I 13.5 A
DM
Continuous Source Current (Body Diode) I 4.0 A
S
Maximum Pulsed Source Current (Body Diode) I 13.5 A
SM
Single Pulse Avalanche Energy (Note 1) E 197 mJ
AS
Power Dissipation P 38 W
D
Operating and Storage Junction Temperature T , T -55 to +150 C
J stg
Thermal Resistance 3.29 C/W
JC
Thermal Resistance 110 C/W
JA
Note 1: L=30mH, I =3.5A, V =100V, R =25, Initial T =25C
AS DD G J
ELECTRICAL CHARACTERISTICS: (T =25C unless otherwise noted)
C
SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
I , I V =30V, V=0 100 nA
GSSF GSSR GS DS
I V =600V, V=0 0.065 1.0 A
DSS DS GS
BV V =0, I=250A 600 V
DSS GS D
V V =V , I=250A 2.0 3.25 4.0 V
GS(th) GS DS D
V V =0, I=4.0A 0.86 1.4 V
SD GS S
r V =10V, I=2.0A 0.65 0.95
DS(ON) GS D
C V =100V, V =0, f=1.0MHz 1.31 pF
rss DS GS
C V =100V, V =0, f=1.0MHz 328 pF
iss DS GS
C V =100V, V =0, f=1.0MHz 26 pF
oss DS GS
R2 (10-August 2015)CDM4-600LR
SURFACE MOUNT SILICON
N-CHANNEL
LR POWER MOSFET
4.0 AMP, 600 VOLT
ELECTRICAL CHARACTERISTICS - Continued: (T =25C unless otherwise noted)
C
SYMBOL TEST CONDITIONS TYP UNITS
Q V =480V, V =10V, I =4.0A (Note 2) 11.59 nC
g(tot) DS GS D
Q V =480V, V =10V, I =4.0A (Note 2) 2.04 nC
gs DS GS D
Q V =480V, V =10V, I =4.0A (Note 2) 6.09 nC
gd DS GS D
t V =300V, V =10V, I =4.0A, R =25 (Note 2) 8.0 ns
d(on) DD GS D G
t V =300V, V =10V, I =4.0A, R =25 (Note 2) 24 ns
r DD GS D G
t V =300V, V =10V, I =4.0A, R =25 (Note 2) 33 ns
d(off) DD GS D G
t V =300V, V =10V, I =4.0A, R =25 (Note 2) 24 ns
f DD GS D G
t V =0, I =4.0A, di/dt=100A/s (Note 2) 211 ns
rr GS S
Q V =0, I =4.0A, di/dt=100A/s (Note 2) 1.7 C
rr GS S
Note 2: Pulse Width < 300s, Duty Cycle < 2%
DPAK CASE - MECHANICAL OUTLINE
PIN CONFIGURATION
LEAD CODE:
1) Gate
2) Drain
3) Source
4) Drain
Pin 2 is common to the tab (4)
MARKING: FULL PART NUMBER
R2 (10-August 2015)
www.centralsemi.com