CDM7-650
SURFACE MOUNT SILICON
www.centralsemi.com
N-CHANNEL
DESCRIPTION:
MEDIUM POWER MOSFET
The CENTRAL SEMICONDUCTOR CDM7-650 is a
7.0 AMP, 650 VOLT
650 volt N-Channel MOSFET designed for high voltage,
fast switching applications such as Power Factor
Correction (PFC), lighting and power inverters. This
MOSFET combines high voltage capability with low
r , low threshold voltage, and low gate charge for
DS(ON)
optimal efficiency.
MARKING: FULL PART NUMBER
DPAK CASE
APPLICATIONS: FEATURES:
Power Factor Correction
High voltage capability (V =650V)
DS
Alternative energy inverters
Low gate charge (Q =5.0nC)
gs
Solid state lighting
Low r (1.35)
DS(ON)
MAXIMUM RATINGS: (T =25C unless otherwise noted)
A
SYMBOL UNITS
Drain-Source Voltage V 650 V
DS
Gate-Source Voltage V 30 V
GS
Continuous Drain Current (Steady State) I 7.0 A
D
Maximum Pulsed Drain Current, tp=10s I 28 A
DM
Continuous Source Current (Body Diode) I 7.0 A
S
Maximum Pulsed Source Current (Body Diode) I 28 A
SM
Single Pulse Avalanche Energy (Note 1) E 435 mJ
AS
Power Dissipation P 1.12 W
D
Power Dissipation (T=25C) P 140 W
C D
Operating and Storage Junction Temperature T , T -55 to +150 C
J stg
Thermal Resistance 0.89 C/W
JC
Thermal Resistance 110 C/W
JA
ELECTRICAL CHARACTERISTICS: (T =25C unless otherwise noted)
A
SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
I , I V =30V, V=0 10 100 nA
GSSF GSSR GS DS
I V =650V, V=0 0.03 1.0 A
DSS DS GS
BV V =0, I=250A 650 V
DSS GS D
V V =V , I=250A 2.0 2.88 4.0 V
GS(th) GS DS D
V V =0, I=7.0A 0.88 1.4 V
SD GS S
r V =10V, I=3.5A 1.35 1.5
DS(ON) GS D
C V =25V, V =0, f=1.0MHz 0.8 pF
rss DS GS
C V =25V, V =0, f=1.0MHz 754 pF
iss DS GS
C V =25V, V =0, f=1.0MHz 97 pF
oss DS GS
Notes: (1) L=30mH, I =5.25A, V =50V, R =25, Initial T =25C
AS DD G J
R2 (2-July 2014)CDM7-650
SURFACE MOUNT SILICON
N-CHANNEL
MEDIUM POWER MOSFET
7.0 AMP, 650 VOLT
ELECTRICAL CHARACTERISTICS - Continued: (T =25C unless otherwise noted)
A
SYMBOL TEST CONDITIONS TYP UNITS
Q V =520V, V =10V, I =7.0A (Note 2) 16.8 nC
g(tot) DS GS D
Q V =520V, V =10V, I =7.0A (Note 2) 5.0 nC
gs DS GS D
Q V =520V, V =10V, I =7.0A (Note 2) 6.0 nC
gd DS GS D
t V =325V, I =7.0A, R =25 (Note 2) 14 ns
d DD D G
t V =325V, I =7.0A, R =25 (Note 2) 28 ns
r DD D G
t V =325V, I =7.0A, R =25 (Note 2) 38 ns
s DD D G
t V =325V, I =7.0A, R =25 (Note 2) 28 ns
f DD D G
t V =0, I =7.0A, di/dt=100A/s (Note 2) 493 ns
rr GS S
Q V =0, I =7.0A, di/dt=100A/s (Note 2) 2.99 C
rr GS S
Notes: (2) Pulse Width < 300s, Duty Cycle < 2%
DPAK CASE - MECHANICAL OUTLINE
PIN CONFIGURATION
LEAD CODE:
1) Gate
2) Drain
3) Source
4) Drain
Pin 2 is common to the tab (4)
MARKING: FULL PART NUMBER
R2 (2-July 2014)
www.centralsemi.com