CMLDM7003TG SURFACE MOUNT www.centralsemi.com DUAL N-CHANNEL DESCRIPTION: ENHANCEMENT-MODE SILICON MOSFET The CENTRAL SEMICONDUCTOR CMLDM7003TG is a dual Enhancement-mode N-Channel MOSFET, manufactured by the N-Channel DMOS Process, designed for high speed pulsed amplifier and driver applications. This device offers low r , low DS(ON) V and ESD protection up to 2kV. GS(th), MARKING CODE: CTG SOT-563 CASE Device is Halogen Free by design MAXIMUM RATINGS: (T =25C) SYMBOL UNITS A Drain-Source Voltage V 50 V DS Drain-Gate Voltage V 50 V DG Gate-Source Voltage V 12 V GS Continuous Drain Current I 280 mA D Maximum Pulsed Drain Current I 1.5 A DM Power Dissipation (Note 1) P 350 mW D Power Dissipation (Note 2) P 300 mW D Power Dissipation (Note 3) P 150 mW D Operating and Storage Junction Temperature T , T -65 to +150 C J stg Thermal Resistance 357 C/W JA ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (T =25C unless otherwise noted) A SYMBOL TEST CONDITIONS MIN TYP MAX UNITS I , I V=5.0V 50 nA GSSF GSSR GS I , I V=10V 0.5 A GSSF GSSR GS I , I V=12V 1.0 A GSSF GSSR GS I V =50V, V=0 50 nA DSS DS GS BV V =0, I=10A 50 V DSS GS D V V =V , I=250A 0.7 1.2 V GS(th) DS GS D V V =0, I=115mA 1.4 V SD GS S r V =1.8V, I=50mA 1.6 2.3 DS(ON) GS D r V =2.5V, I=50mA 1.3 1.9 DS(ON) GS D r V =5.0V, I=50mA 1.1 1.5 DS(ON) GS D g V =10V, I=200mA 200 mS FS DS D C V =25V, V =0, f=1.0MHz 5.0 pF rss DS GS C V =25V, V =0, f=1.0MHz 50 pF iss DS GS C V =25V, V =0, f=1.0MHz 25 pF oss DS GS 2 Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0mm 2 (2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0mm 2 (3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4mm R2 (15-April 2010)CMLDM7003TG SURFACE MOUNT DUAL N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET SOT-563 CASE - MECHANICAL OUTLINE PIN CONFIGURATION LEAD CODE: 1) Gate Q1 MARKING CODE: CTG 2) Source Q1 3) Drain Q2 4) Gate Q2 5) Source Q2 6) Drain Q1 R2 (15-April 2010) www.centralsemi.com