CMLDM7003
CMLDM7003G*
CMLDM7003J
www.centralsemi.com
SURFACE MOUNT SILICON
DESCRIPTION:
DUAL N-CHANNEL
These CENTRAL SEMICONDUCTOR devices
ENHANCEMENT-MODE
are dual N-Channel enhancement-mode MOSFETs,
MOSFETS
manufactured by the N-Channel DMOS Process,
designed for high speed pulsed amplifier and driver
applications. The CMLDM7003 utilizes the USA pinout
configuration, while the CMLDM7003J utilizes the
Japanese pinout configuration. These devices offer low
r and ESD protection up to 2kV.
DS(ON)
MARKING CODES: CMLDM7003: C30
SOT-563 CASE CMLDM7003G*: C3G
CMLDM7003J: C3J
Device is Halogen Free by design
*
MAXIMUM RATINGS: (T =25C) SYMBOL UNITS
A
Drain-Source Voltage V 50 V
DS
Drain-Gate Voltage V 50 V
DG
Gate-Source Voltage V 12 V
GS
Continuous Drain Current I 280 mA
D
Maximum Pulsed Drain Current I 1.5 A
DM
Power Dissipation (Note 1) P 350 mW
D
Power Dissipation (Note 2) P 300 mW
D
Power Dissipation (Note 3) P 150 mW
D
Operating and Storage Junction Temperature T , T -65 to +150 C
J stg
Thermal Resistance 357 C/W
JA
ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (T =25C unless otherwise noted)
A
SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
I I V=5.0V 100 nA
GSSF, GSSR GS
I I V=10V 2.0 A
GSSF, GSSR GS
I I V=12V 2.0 A
GSSF, GSSR GS
I V =50V, V=0 50 nA
DSS DS GS
BV V =0, I=10A 50 V
DSS GS D
V V =V , I=250A 0.49 1.0 V
GS(th) DS GS D
V V =0, I=115mA 1.4 V
SD GS S
r V =1.8V, I=50mA 1.6 3.0
DS(ON) GS D
r V =2.5V, I=50mA 1.3 2.5
DS(ON) GS D
r V =5.0V, I=50mA 1.1 2.0
DS(ON) GS D
g V =10V, I=200mA 200 mS
FS DS D
C V =25V, V =0, f=1.0MHz 5.0 pF
rss DS GS
C V =25V, V =0, f=1.0MHz 50 pF
iss DS GS
C V =25V, V =0, f=1.0MHz 25 pF
oss DS GS
Q V =25V, V =4.5V, I=100mA 0.764 nC
g(tot) DS GS D
Q V =25V, V =4.5V, I=100mA 0.148 nC
gs DS GS D
Q V =25V, V =4.5V, I=100mA 0.156 nC
gd DS GS D
2
Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0mm
2
(2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0mm
2
(3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4mm
R9 (8-June 2015) CMLDM7003
CMLDM7003G*
CMLDM7003J
SURFACE MOUNT SILICON
DUAL N-CHANNEL
ENHANCEMENT-MODE
MOSFETS
SOT-563 CASE - MECHANICAL OUTLINE
PIN CONFIGURATIONS
CMLDM7003J (Japanese Pinout)
CMLDM7003 (USA Pinout)
CMLDM7003G*
LEAD CODE: LEAD CODE:
1) Gate Q1 1) Source Q1
2) Source Q1 2) Gate Q1
3) Drain Q2 3) Drain Q2
4) Gate Q2 4) Source Q2
5) Source Q2 5) Gate Q2
6) Drain Q1 6) Drain Q1
MARKING CODES: MARKING CODE: C3J
CMLDM7003: C30
CMLDM7003G*: C3G
* Device is Halogen Free by design
R9 (8-June 2015)
www.centralsemi.com