CMLDM7484 SURFACE MOUNT SILICON www.centralsemi.com N-CHANNEL AND P-CHANNEL DESCRIPTION: ENHANCEMENT-MODE The CENTRAL SEMICONDUCTOR CMLDM7484 COMPLEMENTARY MOSFET consists of complementary N-Channel and P-Channel enhancement-mode silicon MOSFETs designed for high speed pulsed amplifier and driver applications. These MOSFETs offer very low r and low DS(ON) threshold voltage. MARKING CODE: 8C7 FEATURES: SOT-563 CASE ESD Protection up to 2kV 350mW Power Dissipation Very Low r DS(ON) APPLICATIONS: Low Threshold Voltage Load/Power Switches Logic Level Compatible Power Supply Converter Circuits Small, SOT-563 Surface Mount Package Battery Powered Portable Devices MAXIMUM RATINGS: (T =25C) SYMBOL UNITS A Drain-Source Voltage V 30 V DS Gate-Source Voltage V 8.0 V GS Continuous Drain Current I 450 mA D Power Dissipation (Note 1) P 350 mW D Power Dissipation (Note 2) P 300 mW D Power Dissipation (Note 3) P 150 mW D Operating and Storage Junction Temperature T , T -65 to +150 C J stg Thermal Resistance (Note 1) 357 C/W JA ELECTRICAL CHARACTERISTICS: (T =25C) N-CH (Q1) P-CH (Q2) A SYMBOL TEST CONDITIONS MIN MAX MIN MAX UNITS I , I V =8.0V, V=0 - 3.0 - 3.0 A GSSF GSSR GS DS I V =30V, V=0 - 1.0 - 1.0 A DSS DS GS BV V =0, I=10A 30 - - - V DSS GS D BV V =0, I=100A - - 30 - V DSS GS D V V =V , I=250A 0.5 1.0 0.5 1.0 V GS(th) DS GS D V V =0, I=400mA 0.5 1.1 - - V SD GS S V V =0, I=100mA - - 0.5 1.1 V SD GS S r V =4.5V, I=200mA - 0.46 - - DS(ON) GS D r V =4.5V, I=430mA - - - 1.1 DS(ON) GS D r V =2.5V, I=100mA - 0.56 - - DS(ON) GS D r V =2.5V, I=200mA - - - 2.0 DS(ON) GS D r V =1.8V, I=75mA - 0.73 - - DS(ON) GS D r V =1.8V, I=100mA - - - 3.3 DS(ON) GS D 2 Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0mm 2 (2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0mm 2 (3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4mm R5 (8-June 2015)CMLDM7484 SURFACE MOUNT SILICON N-CHANNEL AND P-CHANNEL ENHANCEMENT-MODE COMPLEMENTARY MOSFET ELECTRICAL CHARACTERISTICS - Continued: (T =25C) N-CH (Q1) P-CH (Q2) A SYMBOL TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS g V =10V, I =100mA 200 - - 200 - - mS FS DS D C V =25V, V =0, f=1.0MHz - - 10 - - 10 pF rss DS GS C V =25V, V =0, f=1.0MHz - - 45 - - 55 pF iss DS GS C V =25V, V =0, f=1.0MHz - - 15 - - 15 pF oss DS GS Q V =15V, V =4.5V I=1.0A - 0.792 - - - - nC g(tot) DS GS D Q V =10V, V =4.5V I=1.0A - - - - 0.88 - nC g(tot) DS GS D Q V =15V, V =4.5V I=1.0A - 0.15 - - - - nC gs DS GS D Q V =10V, V =4.5V I=1.0A - - - - 0.35 - nC gs DS GS D Q V =15V, V =4.5V I=1.0A - 0.23 - - - - nC gd DS GS D Q V =10V, V =4.5V I=1.0A - - - - 0.128 - nC gd DS GS D SOT-563 CASE - MECHANICAL OUTLINE PIN CONFIGURATION LEAD CODE: 1) Source Q1 2) Gate Q1 3) Drain Q2 4) Source Q2 5) Gate Q2 6) Drain Q1 MARKING CODE: 8C7 R5 (8-June 2015) www.centralsemi.com