CMLDM7585 SURFACE MOUNT SILICON www.centralsemi.com N-CHANNEL AND P-CHANNEL DESCRIPTION: ENHANCEMENT-MODE The CENTRAL SEMICONDUCTOR CMLDM7585 COMPLEMENTARY MOSFETS consists of complementary N-Channel and P-Channel enhancement-mode silicon MOSFETs designed for high speed pulsed amplifier and driver applications. These MOSFETs offer very low r and low DS(ON) threshold voltage. MARKING CODE: 87C FEATURES: ESD protection up to 1800V (Human Body Model) SOT-563 CASE 350mW power pissipation Very low r DS(ON) APPLICATIONS: Low threshold voltage Load/Power switches Logic level compatible Power supply converter circuits Small, SOT-563 surface mount package Battery powered portable devices MAXIMUM RATINGS: (T =25C) SYMBOL N-CH (Q1) P-CH (Q2) UNITS A Drain-Source Voltage V 20 V DS Gate-Source Voltage V 8.0 V GS Continuous Drain Current (Steady State) I 650 mA D Maximum Pulsed Drain Current (tp=10s) I 1.3 1.0 A DM Power Dissipation (Note 1) P 350 mW D Power Dissipation (Note 2) P 300 mW D Power Dissipation (Note 3) P 150 mW D Operating and Storage Junction Temperature T , T -65 to +150 C J stg Thermal Resistance (Note 1) 357 C/W JA ELECTRICAL CHARACTERISTICS: (T =25C) N-CH (Q1) P-CH (Q2) A SYMBOL TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS I , I V =4.5V, V =0 - - 1.0 - - 10 A GSSF GSSR GS DS I V =16V, V =0 - - 100 - - 100 nA DSS DS GS BV V =0, I=250A 20 - - 20 - - V DSS GS D V V =V , I=250A 0.5 - 1.1 0.5 - 1.0 V GS(th) DS GS D V V =0, I=200mA - - 1.1 - - - V SD GS S V V =0, I=250mA - - - - - 1.1 V SD GS S r V =4.5V, I=600mA - 0.14 0.23 - - - DS(ON) GS D r V =4.5V, I=350mA - - - - 0.25 0.36 DS(ON) GS D r V =2.5V, I=500mA - 0.2 0.275 - - - DS(ON) GS D r V =2.5V, I=300mA - - - - 0.37 0.5 DS(ON) GS D r V =1.8V, I=350mA - - 0.7 - - - DS(ON) GS D r V =1.8V, I=150mA - - - - - 0.8 DS(ON) GS D 2 Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0mm 2 (2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0mm 2 (3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4mm R4 (5-June 2013)CMLDM7585 SURFACE MOUNT SILICON N-CHANNEL AND P-CHANNEL ENHANCEMENT-MODE COMPLEMENTARY MOSFETS ELECTRICAL CHARACTERISTICS - Continued: (T =25C) N-CH (Q1) P-CH (Q2) A SYMBOL TEST CONDITIONS MIN TYP MIN TYP UNITS g V =10V, I=400mA 1.0 - - - S FS DS D g V =10V, I=200mA - - 0.2 - S FS DS D C V =16V, V =0, f=1.0MHz - 18 - 25 pF rss DS GS C V =16V, V =0, f=1.0MHz - 100 - 100 pF iss DS GS C V =16V, V =0, f=1.0MHz - 16 - 21 pF oss DS GS Q V =10V, V =4.5V, I=500mA - 1.58 - - nC g(tot) DS GS D Q V =10V, V =4.5V, I=200mA - - - 1.2 nC g(tot) DS GS D Q V =10V, V =4.5V, I=500mA - 0.17 - - nC gs DS GS D Q V =10V, V =4.5V, I=200mA - - - 0.24 nC gs DS GS D Q V =10V, V =4.5V, I=500mA - 0.24 - - nC gd DS GS D Q V =10V, V =4.5V, I=200mA - - - 0.36 nC gd DS GS D t V =10V, V =4.5V, I =200mA, R=10 - 10 - 38 ns on DD GS D G t V =10V, V =4.5V, I =200mA, R=10 - 25 - 48 ns off DD GS D G SOT-563 CASE - MECHANICAL OUTLINE PIN CONFIGURATION LEAD CODE: 1) Source Q1 2) Gate Q1 3) Drain Q2 4) Source Q2 5) Gate Q2 6) Drain Q1 MARKING CODE: 87C R4 (5-June 2013) www.centralsemi.com