CS8952 CrystalLAN 100BASE-X and 10BASE-T Transceiver Features Description z Single-Chip IEEE 802.3 Physical Interface IC for The CS8952 uses CMOS technology to deliver a high- 100BASE-TX, 100BASE-FX and 10BASE-T performance, low-cost 100BASE-X/10BASE-T Physical z Adaptive Equalizer provides Extended Length Layer (PHY) line interface. It makes use of an adaptive Operation (>160 m) with Superior Noise equalizer optimized for noise and near end crosstalk Immunity and NEXT Margin (NEXT) immunity to extend receiver operation to cable z Extremely Low Transmit Jitter (<400 ps) lengths exceeding 160 m. In addition, the transmit cir- z Low Common Mode Noise on TX Driver for cuitry has been designed to provide extremely low Reduced EMI Problems transmit jitter (<400 ps) for improved link partner perfor- mance. Transmit driver common mode noise has been z Integrated RX and TX Filters for 10BASE-T minimized to reduce EMI for simplified FCC certification. z Compensation for Back-to-Back Killer Packets z Digital Interfaces Supported The CS8952 incorporates a standard Media Indepen- Media Independent Interface (MII) for 100BASE-X dent Interface (MII) for easy connection to a variety of 10 and 10BASE-T and 100 Mb/s Media Access Controllers (MACs). The Repeater 5-bit code-group interface (100BASE-X) CS8952 also includes a pseudo-ECL interface for use 10BASE-T Serial Interface with 100Base-FX fiber interconnect modules. z Register Set Compatible with DP83840A ORDERING INFORMATION z IEEE 802.3 Auto-Negotiation with Next Page Support See Ordering Information on page 80. z Six LED drivers (LNK, COL, FDX, TX, RX, and SPD) z Low power (135 mA Typ) CMOS design operates on a single 5 V supply CS8952 10BaseT/100Base-X 10/100 Transceiver Manchester 10BaseT TX EN Encoder Filter M TX ER/TXD4 TX+, U TXD 3:0 TX- X 4B/5B MLT-3 Slew Rate TX CLK Scrambler Encoder Encoder Control Fiber NRZI TX NRZ+, ECL Driver Interface TX NRZ- MDC Fiber NRZI RX NRZ+, MII IRQ ECL Receiver Interface RX NRZ- MDIO 10/100 Adaptive Eq. & 4B/5B MLT-3 100BaseT Descrambler Baseline Wander Decoder Decoder Slicer M Compensation RX+, U CRS RX- X COL Manchester 10BaseT 10BaseT Decoder Slicer Filter RX ER/RXD4 RX DV RXD 3:0 LED1 RX CLK MII LED2 Link Timing Auto LED RX EN Control/Status LED3 Management Recovery Negotiation Drivers Registers LED4 LED5 Copyright Cirrus Logic, Inc. 2007 CS8952 TABLE OF CONTENTS 1. SPECIFICATIONS AND CHARACTERISTICS......................................................... 3 2. INTRODUCTION ..................................................................................................... 18 2.1 High Performance Analog............................................................................. 18 2.2 Low Power Consumption .............................................................................. 18 2.3 Application Flexibility..................................................................................... 18 2.4 Typical Connection Diagram......................................................................... 18 3. FUNCTIONAL DESCRIPTION ................................................................................ 18 3.1 Major Operating Modes................................................................................. 20 3.1.1 100BASE-X MII Application (TX and FX) ........................................... 20 Symbol Encoding and Decoding ........................................................... 20 100 Mb/s Loopback ............................................................................... 22 3.1.2 100BASE-X Repeater Application ...................................................... 22 3.1.3 10BASE-T MII Application .................................................................. 23 Full and Half Duplex operation .............................................................. 23 Collision Detection ................................................................................ 23 Jabber ................................................................................................... 23 Link Pulses ............................................................................................ 23 Receiver Squelch .................................................................................. 23 10BASE-T Loopback ............................................................................. 23 Carrier Detection ................................................................................... 24 3.1.4 10BASE-T Serial Application .............................................................. 24 3.2 Auto-Negotiation ........................................................................................... 24 3.3 Reset Operation............................................................................................ 25 3.4 LED Indicators............................................................................................... 25 4. MEDIA INDEPENDENT INTERFACE (MII) ............................................................. 25 4.1 MII Frame Structure ...................................................................................... 26 4.2 MII Receive Data........................................................................................... 26 4.3 MII Transmit Data.......................................................................................... 27 4.4 MII Management Interface ............................................................................ 27 4.5 MII Management Frame Structure ................................................................ 28 5. CONFIGURATION .................................................................................................. 29 5.1 Configuration At Power-up/Reset Time......................................................... 29 5.2 Configuration Via Control Pins...................................................................... 29 5.3 Configuration via the MII ............................................................................... 29 6. CS8952 REGISTERS .............................................................................................. 30 7. DESIGN CONSIDERATIONS .................................................................................. 62 7.1 Twisted Pair Interface ................................................................................... 62 7.2 100BASE-FX Interface.................................................................................. 62 7.3 Internal Voltage Reference ........................................................................... 63 7.4 Clocking Schemes ........................................................................................ 63 7.5 Recommended Magnetics ............................................................................ 64 7.6 Power Supply and Decoupling...................................................................... 64 7.7 General Layout Recommendations............................................................... 65 8. PIN DESCRIPTIONS ............................................................................................... 67 9. PACKAGE DIMENSIONS..................................................................................... 79 10. ORDERING INFORMATION ................................................................................. 80 11. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ........... 80 12. REVISION HISTORY ............................................................................................ 81 CrystalLAN 100BASE-X and 10BASE-T Transceiver 2 DS206F1