HXNV01600 16 Megabit Non-Volatile Magneto-Resistive RAM Features Fabricated on S150 Silicon On Insulator (SOI) CMOS Underlayer Technology 150 nm Process Total Dose Hardness 6 1x10 rad (Si) Dose Rate Upset Hardness 10 1x10 rad(Si)/s Dose Rate Survivability 12 1x10 rad(Si)/s Soft Error Rate -10 1x10 upsets/bit-day Neutron Hardness 14 2 1x10 N/cm No Latchup Read Access Time The Honeywell 16 Megabit radiation hardened low power non-volatile Magneto-Resistive 95 ns Random Access Memory (MRAM) offers high performance and is designed for spa ce and Read Cycle Time military applications. The part can be congured as either a 2,097,152 word x 8- bit or a 120 ns 1,048,576 word x 16 bit MRAM through an external pin setting. Write Cycle Time 140 ns The high reliability MRAM is designed for Fabricated with Honeywells radiation Robust Write and Read Capability severe space environments and features hardened Silicon On Insulator (SOI) 15 years Data Retention 105C excellent endurance, integrated Error technology, the MRAM is designed for Synchronous Operation Correction Coding (ECC) and low-vo ltage use in low-voltage systems operating Address Auto Increment Feature write protection. These features ensure in radiation environments over a tempera- Single-Bit Error Detection & the correct operation of the memory and ture range of -40C to +125C with a Correction (ECC) protection from inadvertent writes. 3.3 0.3V power supply. Power Supply 3.3V 0.3V Functional Block Diagram 3.3V CMOS Compatible I/O Standard Operating CE B D Q CLK Temperature Range is CLK Data Array ECC Array -40C to +125C A 19:8 A 20:0 262,144 x 64 262,144 x 7 D Q 0 CLK Package: 76 Lead Shielded AUTO INCR CLK Ceramic Quad Flat Pack D Q 1 CLK Standard Microelectronics Data Column ECC Column OVERFLOW I Datasheet 5962-13212 Mux Mux D Q A 7:2 CLK R O Read Write Read Write QML Q and V planned for Q2 2014 A 20,1:0 INIT D Q Byte Mux, Control, and ECC Logic CLK DONE D Q D Q D Q CLK CLK CLK WE 0 D Q DQ 7:0 CLK OE 1 D Q CLK X8 DQ 15:8 OVERFLOW O 21 Bit Counter Col Decode Row DecodePackage Pinout Note: See Signal Description table for proper board connection for TESTIN and TESTOUT pins. VSS 58 38 VSS A 16 59 37 A 15 A 14 60 36 A 13 A 12 61 35 A 11 A 10 62 34 DONE VDD3 63 33 VDD3 A 8 64 32 INIT A 6 65 31 OE CLK 66 30 CE B HXNV01600 WE 67 29 A 9 A 4 68 28 A 7 A 2 69 27 A 5 AUTO INCR 70 26 A 3 VDD3 71 25 VDD3 X8 72 24 A 1 A 0 73 23 OVERFLOW I DQ 0 74 22 OVERFLOW O DQ 1 75 21 DQ 4 VSS 76 20 VSS Signal Description CLK Clock Input. (Rising Edge triggers a memory operation) CE B Chip Enable Bar. Low value enables chip while a high value disables further read/write operations and the data bus goes to high impedance . A(20:0) DQ(15:0) Data Input/Output Signals. Bi-directional data pins which serve as data outputs during a read operation and as data inputs during a write operation. When in X8 mode, only DQ(7:0) are active and DQ(15:8) pins should be tied to VSS. WE Write Enable. Active high write enable. High state at rising edge of CLK initiates a write cycle. Low state at rising edge of CLK initiates a read cycle. OE Output Enable. Active high output enable. Low state puts outputs in high impedance state. X8 AUTO INCR Auto Increment Mode Enable. When high enables internal counter and read only mode. OVERFLOW I Counter Enable Input Pin. Active High Enable for internal counter (when INIT=1,DONE=0). Used to daisy chain devices. INIT Active High Interface Pin used to reset internal address counter (when OVERFLOW I=1, DONE=0) DONE Active Low Interface Pin used to reset internal address counter (when OVERFLOW I=1, INIT=1). OVERFLOW O reached last address. Used to daisy chain devices. VSS Ground VDD3 DC Power Source Input: nominal 3.30V TESTINx TESTOUTx Testout pins shall be treated as no connects and have no connection on the circuit board. Functional Truth Table CLK CE B WE AUTO INCR INIT DONE OVERFLOW I FUNCTION R 0 0 0 X X X Read Cycle (1) R 0 1 0 X X X Write Cycle (1) R 1 X X X X X Chip Disable R 0 X 1 1 0 1 AI Read Cycle (2) (3) R X X 1 0 X X Chip Disable (2) (4) R X X 1 X 1 X Chip Disable (2) (4) R X X 1 X X 0 Chip Disable (2) (4) (1) Read and Write occurs at memory location provide by Address Pins at rising edge of CLK (2) Auto Increment Read Modes (3) Internal Address Counter Starts with Address = 0x00000 and increments 1 per rising edge of CLK (4) Internal Counter Reset to Address = 0x000000 2 57 VSS VSS 1 56 TESTOUT7 TESTIN1 VSS 2 55 DQ 8 TESTIN2 VDD3 3 54 DQ 9 TESTIN3 VSS 4 53 DQ 10 DQ 3 5 52 VDD3 VDD3 6 51 DQ 11 DQ 2 7 50 A 20 TESTOUT1 8 49 A 18 TESTOUT2 9 48 TESTOUT6 TESTOUT3 10 47 A 17 TESTOUT4 11 46 A 19 DQ 5 12 45 TESTOUT5 DQ 6 13 44 VDD3 VDD3 14 43 DQ 15 DQ 7 15 42 DQ 14 TESTIN4 VSS 16 41 DQ 13 TESTIN5 VSS 17 40 DQ 12 TESTIN6 VSS 18 39 VSS VSS 19