Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY7C604XX enCoRe V Low Voltage Microcontroller enCoRe V Low Voltage Microcontroller Internal low-speed oscillator at 32 kHz for watchdog and Features sleep. The frequency range is 19 to 50 kHz with a 32 kHz typical value Powerful Harvard Architecture processor M8C processor speeds running up to 24 MHz Programmable pin configurations Low power at high processing speeds Up to 36 GPIO (depending on package) Interrupt controller 25 mA sink current on all GPIO 1.71 V to 3.6 V operating voltage Pull-up, High Z, open drain, CMOS drive modes on all GPIO Commercial temperature range: 0 C to +70 C CMOS drive mode (5 mA source current) on Ports 0 and 1: 20 mA (at 3.0 V) total source current Flexible on-chip memory Low dropout voltage regulator for Port 1 pins: Up to 32 K flash program storage Programmable to output 3.0, 2.5, or 1.8V 50,000 erase and write cycles Selectable, regulated digital I/O on Port 1 Flexible protection modes Configurable input threshold for Port 1 Up to 2048 bytes SRAM data storage Hot-swappable capability on Port 1 In-system serial programming (ISSP) Additional system resources Complete development tools Configurable communication speeds Free development tool (PSoC Designer) 2 I C Slave Full-featured, in-circuit emulator and programmer Selectable to 50 kHz, 100 kHz, or 400 kHz Full-speed emulation Implementation requires no clock stretching Complex breakpoint structure Implementation during sleep modes with less than 100 mA 128 K trace memory Hardware address detection Precision, programmable clocking SPI master and SPI slave Crystal-less oscillator with support for an external crystal or Configurable between 46.9 kHz and 12 MHz resonator Three 16-bit timers Internal 5.0% 6, 12, or 24 MHz main oscillator 10-bit ADC used to monitor battery voltage or other signals with external components Watchdog and sleep timers Integrated supervisory circuit enCoRe V LV Block Diagram Port 4 Port 3 Port 2 Port 1 Port 0 Prog. LDO enCoRe V CORE System Bus SRAM 8 K / 16 K / 32 K 2048 Bytes SROM Flash Sleep and (M8C) CPU Core Interrupt Watchdog Controller 6 / 12 / 24 MHz Internal Main Oscillator POR and LVD 3 16-Bit I2C Slave/SPI ADC Timers Master-Slave System Resets System Resources Errata: For information on silicon errata, see Errata on page 35. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-12395 Rev. *Q Revised August 10, 2017