CY7C64713 EZ-USB FX1 USB Microcontroller Full Speed USB Peripheral Controller EZ-USB FX1 USB Microcontroller Full Speed USB Peripheral Controller Up to 48 MHz clock rate Features Four clocks for each instruction cycle Single chip integrated USB transceiver, SIE, and enhanced Two USARTS 8051 microprocessor Three counters or timers Fit, form, and function upgradable to the FX2LP (CY7C68013A) Expanded interrupt system Pin compatible Two data pointers Object code compatible 3.3 V operation with 5 V tolerant inputs Functionally compatible (FX1 functionality is a subset of the FX2LP) Smart SIE Draws no more than 65 mA in any mode, making the FX1 Vectored USB interrupts suitable for bus powered applications Separate data buffers for the setup and DATA portions of a Software: 8051 runs from internal RAM, which is: CONTROL transfer Downloaded using USB 2 Integrated I C controller, running at 100 or 400 KHz Loaded from EEPROM 48 MHz, 24 MHz, or 12 MHz 8051 operation External memory device (128 pin configuration only) Four integrated FIFOs 16 KB of on-chip code/data RAM Brings glue and FIFOs inside for lower system cost Four programmable BULK/INTERRUPT/ISOCHRONOUS Automatic conversion to and from 16-bit buses endpoints Master or slave operation Buffering options: double, triple, and quad FIFOs can use externally supplied clock or asynchronous Additional programmable (BULK/INTERRUPT) 64-byte strobes endpoint Easy interface to ASIC and DSP ICs 8- or 16-bit external data interface Vectored for FIFO and GPIF Interrupts Smart media standard ECC generation Up to 40 general purpose IOs (GPIO) GPIF Four package options: Allows direct connection to most parallel interfaces 8- and 16-bit 128-pin TQFP Programmable waveform descriptors and configuration 100-pin TQFP registers to define waveforms 56-pin SSOP Supports multiple ready (RDY) inputs and Control (CTL) 56-pin QFN Pb-free outputs Integrated, industry standard 8051 with enhanced features: Errata: For information on silicon errata, see Errata on page 71. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-08039 Rev. *L Revised March 9, 2014CY7C64713 Logic Block Diagram High performance micro 24 MHz using standard tools Ext. XTAL with lower-power options FX1 2 /0.5 I C 8051 Core x20 Master VCC /1.0 12/24/48 MHz, PLL /2.0 four clocks/cycle Abundant I/O Additional IOs (24) 1.5k including two USARTS connected for enumeration General ADDR (9) programmable I/F D+ to ASIC/DSP or bus GPIF USB standards such as CY 16 KB RDY (6) ATAPI, EPP, etc. CTL (6) D RAM ECC Smart XCVR USB Integrated Engine full speed XCVR Up to 96 MBytes 4 kB 8/16 burst rate FIFO Enhanced USB core Soft Configuration FIFO and endpoint memory Simplifies 8051 code Easy firmware changes (master or slave operation) Document Number: 38-08039 Rev. *L Page 2 of 74 Address (16) Address (16) / Data Bus (8) Data (8)