CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A EZ-USB FX2LP USB Microcontroller High-Speed USB Peripheral Controller EZ-USB FX2LP USB Microcontroller High Speed USB Peripheral Controller Features USB 2.0 USB IF high speed certified (TID 40460272) 3.3 V operation with 5 V tolerant inputs Single chip integrated USB 2.0 transceiver, smart SIE, and Vectored USB interrupts and GPIF/FIFO interrupts enhanced 8051 microprocessor Separate data buffers for the setup and data portions of a Fit, form, and function compatible with the FX2 CONTROL transfer Pin compatible 2 Integrated I C controller, runs at 100 or 400 kHz Object code compatible Four integrated FIFOs Functionally compatible (FX2LP is a superset) Integrated glue logic and FIFOs lower system cost Ultra low power: I No more than 85 mA in any mode CC Automatic conversion to and from 16-bit buses Ideal for bus and battery powered applications Master or slave operation Software: 8051 code runs from: Uses external clock or asynchronous strobes Internal RAM, which is downloaded through USB Easy interface to ASIC and DSP ICs Internal RAM, which is loaded from EEPROM Available in commercial and industrial temperature grade External memory device (128 pin package) (all packages except VFBGA) 16 KB of on-chip code/data RAM Features (CY7C68013A/14A only) Four programmable BULK, INTERRUPT, and CY7C68014A: Ideal for Battery Powered Applications ISOCHRONOUS endpoints Suspend current: 100 A (typ) Buffering options: Double, triple, and quad CY7C68013A: Ideal for Non Battery Powered Applications Additional programmable (BULK/INTERRUPT) 64-byte Suspend current: 300 A (typ) endpoint Available in Five Pb-free Packages with Up to 40 GPIOs 8-bit or 16-bit external data interface 128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin Smart media standard ECC generation QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin VFBGA (24 GPIOs) GPIF (general programmable interface) Enables direct connection to most parallel interfaces Features (CY7C68015A/16A only) Programmable waveform descriptors and configuration CY7C68016A: Ideal for Battery Powered Applications registers to define waveforms Suspend current: 100 A (typ) Supports multiple ready (RDY) inputs and Control (CTL) outputs CY7C68015A: Ideal for Non Battery Powered Applications Integrated, industry standard enhanced 8051 Suspend current: 300 A (typ) 48 MHz, 24 MHz, or 12 MHz CPU operation Available in Pb-free 56-pin QFN Package (26 GPIOs) Four clocks per instruction cycle Two more GPIOs than CY7C68013A/14A enabling additional Two USARTs features in same footprint Three counter/timers Expanded interrupt system Two data pointers Errata: For information on silicon errata, see Errata on page 64. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-08032 Rev. *W Revised July 19, 2013 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Logic Block Diagram High performance micro 24 MHz using standard tools Ext. XTAL with lower-power options FX2LP 2 /0.5 I C 8051 Core x20 Master VCC /1.0 12/24/48 MHz, PLL /2.0 four clocks/cycle Abundant I/O Additional I/Os (24) 1.5k including two USARTs connected for full speed General ADDR (9) programmable I/F D+ to ASIC/DSP or bus GPIF USB standards such as CY 16 KB RDY (6) 2.0 CTL (6) ATAPI, EPP, etc. Smart D RAM ECC XCVR USB 1.1/2.0 Integrated Engine full speed and Up to 96 MBytes/s high speed 4 kB 8/16 burst rate XCVR FIFO Enhanced USB core Soft Configuration FIFO and endpoint memory Simplifies 8051 code Easy firmware changes (master or slave operation) Cypresss EZ-USB FX2LP (CY7C68013A/14A) is a low than USB 2.0 SIE or external transceiver implementations. With power version of the EZ-USB FX2(CY7C68013), which is a EZ-USB FX2LP, the Cypress Smart SIE handles most of the highly integrated, low power USB 2.0 microcontroller. By USB 1.1 and 2.0 protocol in hardware, freeing the embedded integrating the USB 2.0 transceiver, serial interface engine (SIE), microcontroller for application specific functions and decreasing enhanced 8051 microcontroller, and a programmable peripheral development time to ensure USB compatibility. interface in a single chip, The General Programmable Interface (GPIF) and Master/Slave Cypress has created a cost effective solution that provides Endpoint FIFO (8-bit or 16-bit data bus) provides an easy and superior time-to-market advantages with low power to enable glueless interface to popular interfaces such as ATA, UTOPIA, bus powered applications. EPP, PCMCIA, and most DSP/processors. The ingenious architecture of FX2LP results in data transfer The FX2LP draws less current than the FX2 (CY7C68013), has rates of over 53 Mbytes per second, the maximum allowable double the on-chip code/data RAM, and is fit, form and function USB 2.0 bandwidth, while still using a low cost 8051 compatible with the 56, 100, and 128 pin FX2. microcontroller in a package as small as a 56 VFBGA (5 mm x 5 Five packages are defined for the family: 56 VFBGA, 56 SSOP, mm). Because it incorporates the USB 2.0 transceiver, the 56 QFN, 100 TQFP, and 128 TQFP. FX2LP is more economical, providing a smaller footprint solution Document Number: 38-08032 Rev. *W Page 2 of 68 Address (16) Address (16) / Data Bus (8) Data (8)