CY7C68033 CY7C68034 EZ-USB NX2LP-Flex Flexible USB NAND Flash Controller EZ-USB NX2LP-Flex Flexible USB NAND Flash Controller Integrated, industry-standard enhanced 8051 CY7C68033/CY7C68034 Silicon Features 48-MHz, 24-MHz, or 12-MHz CPU operation Certified compliant for bus- or self-powered USB 2.0 operation Four clocks for each instruction cycle (TID 40490118) Three counter/timers Expanded interrupt system Single-chip, integrated USB 2.0 transceiver and smart SIE Two data pointers Ultra low power 43 mA typical current draw in any mode 3.3-V operation with 5 V tolerant inputs Enhanced 8051 core Vectored USB interrupts and GPIF/FIFO interrupts Firmware runs from internal RAM that is downloaded from NAND Flash at startup Separate data buffers for the setup and data portions of a No external EEPROM required control transfer 2 15 KBytes of on-chip code/data RAM Integrated I C controller, runs at 100 or 400 kHz Default NAND firmware 8 kB Four integrated FIFOs Default free space 7 kB Integrated glue logic and FIFOs lower system cost Four programmable bulk/interrupt/isochronous endpoints Automatic conversion to and from 16-bit buses Buffering options: double, triple, and quad Master or slave operation Uses external clock or asynchronous strobes Additional programmable (bulk/interrupt) 64-byte endpoint Easy interface to ASIC and DSP ICs SmartMedia standard hardware ECC generation with 1-bit Available in space saving 56-pin QFN package correction and 2-bit detection General programmable interface (GPIF) CY7C68034 Only Silicon Features Enables direct connection to most parallel interfaces Ideal for battery powered applications Programmable waveform descriptors and configuration Suspend current: 100 A (typ) registers to define waveforms Supports multiple ready (RDY) inputs and control (CTL) CY7C68033 Only Silicon Features outputs Ideal for non-battery powered applications 12 fully programmable general purpose I/O (GPIO) pins Suspend current: 300 A (typ) Logic Block Diagram High-performance, 24 MHz enhanced 8051 core Ext. Xtal with low power options NX2LP-Flex /0.5 8051 Core x 20 /1.0 2 12/24/48 MHz, PLL I C /2.0 four clocks/cycle Master V CC Connected for Additional I/Os 1.5k full speed USB NAND General Programmable Boot Logic I/F to ASIC/DSP or bus (ROM) standards such as 8-bit GPIF NAND, EPP, and so on. RDY (2) USB D+ 15 kB CTL (3) CY ECC 2.0 Smart RAM D XCVR USB 1.1/2.0 Up to 96 MB/s burst rate Engine Integrated full- and high speed XCVR 4 kB 8/16 FIFO Soft Configuration enables FIFO and USB endpoint memory Enhanced USB core easy firmware changes simplifies 8051 code (master or slave modes) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-04247 Rev. *O Revised May 30, 2017 Address (16)/Data Bus (8)CY7C68033 CY7C68034 Industry standard (SmartMedia) page management for wear Default NAND Firmware Features leveling algorithm, bad block handling, and physical to logical Because the NX2LP-Flex is intended for NAND Flash-based management. USB mass storage applications, a default firmware image is included in the development kit with the following features: 8-bit NAND Flash interface support High-Speed (480 Mbps) or Full-Speed (12 Mbps) USB support Support for 30 ns, 50 ns, and 100 ns NAND Flash timing NAND sizes supported per chip select Complies with the USB mass storage class specification revision 1.0 512 bytes for up to 1 Gb capacity 2K bytes for up to 8 Gb capacity The default firmware image implements a USB 2.0 NAND Flash 4K bytes for up to 16 Gb capacity controller. This controller adheres to the Mass Storage Class Bulk-Only Transport Specification. The USB port of the 12 configurable GPIO pins NX2LP-Flex is connected to a host computer directly or through Two dedicated chip enable (CE ) pins the downstream port of a USB hub. The host software issues Six configurable CE /GPIO pins commands and data to the NX2LP-Flex and receives status and Up to eight NAND Flash single-device (single-die) chips data from the NX2LP-Flex using standard USB protocol. are supported The default firmware image supports industry leading 8-bit Up to four NAND Flash dual-device (dual-die) chips are NAND Flash interfaces and both common NAND page sizes of supported 512 and 2k bytes. Up to eight CE pins enable the NX2LP-Flex Compile option enables unused CE pins to be configured to be connected to up to eight single or four dual-die NAND Flash as GPIOs chips. Four dedicated GPIO pins Complete source code and documentation for the default firmware image are included in the NX2LP-Flex development kit Industry-standard ECC NAND flash correction to enable customization for meeting design requirements. 1-bit error correction for every 256 bytes Additionally, compile options for the default firmware enable 2-bit error detection for every 256 bytes quick configuration of some features to decrease design effort and increase time-to-market advantages. Document Number: 001-04247 Rev. *O Page 2 of 40