Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comEZ-PD CCG2 Datasheet USB Type-C Port Controller USB Type-C Port Controller General Description EZ-PD CCG2 is a USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG2 provides a complete USB Type-C and U1SB Power Delivery port control solution for passive cables, active cables, and powered accessories. It can also be used in many upstream and downstream facing port applications. EZ-PD CCG2 uses Cypresss proprietary M0S8 technology with a 32-bit, 48-MHz Arm Cortex -M0 processor with 32-KB flash and integrates a complete Type-C Transceiver including the Type-C termination resistors R , R and R . P D A Type-C Support Applications Integrated transceiver (baseband PHY) USB Type-C EMCA cables Integrated UFP (R ), EMCA (R ) termination resistors, and D A USB Type-C powered accessories current sources for DFP (R ) P USB Type-C upstream facing ports Supports one USB Type-C port USB Type-C downstream facing ports Low-Power Operation Features 2.7-V to 5.5-V operation Two independent VCONN rails with integrated isolation 32-bit MCU Subsystem between the two 48-MHz ARM Cortex-M0 CPU Independent supply voltage pin for GPIO that allows 1.71-V to 32-KB Flash 5.5-V signaling on the I/Os 4-KB SRAM Reset: 1.0 A, Deep Sleep: 2.5 A, Sleep: 2.0 mA In-system reprogrammable System-Level ESD on CC and VCONN Pins Integrated Digital Blocks 8-kV Contact Discharge and 15-kV Air Gap Discharge based Integrated timers and counters to meet response times on IEC61000-4-2 level 4C required by the USB-PD protocol Packages Run-time reconfigurable serial communication block (SCB) 2 1.63 mm 2.03 mm, 20-ball wafer-level CSP (WLCSP) with with reconfigurable I C, SPI, or UART functionality 0.4-mm ball pitch Clocks and Oscillators 2.5 mm 3.5 mm 0.6 mm 14-pin DFN Integrated oscillator eliminating the need for external clock 4.0 mm 4.0 mm, 0.55 mm 24-pin QFN Supports industrial (40 C to +85 C) and extended industrial ( 40 C to +105 C) temperature ranges Logic Block Diagram CCG2: USB Type-C Cable Controller MCU Subsystem I/O Subsystem Integrated Digital Blocks 5 CC 1 TCPWM VCONN1 2 SCB 2 (I C, SPI, UART) CORTEX-M0 VCONN2 2 SCB 48 MHz 2 (I C, SPI, UART) VDDIO 6 GPIO Profiles and Port Configurations Flash Baseband MAC (32 KB) Baseband PHY SRAM 3 4 Integrated R , R , d a (4 KB) 7 and R p Serial Wire Debug 1 Timer, counter, pulse-width modulation block 2 2 Serial communication block configurable as UART, SPI, or I C 3 Termination resistor denoting a UFP 4 Termination resistor denoting an EMCA 5 Configuration Channel 6 General-purpose input/output 7 Current Sources to indicate a DFP Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-93912 Rev. *N Revised December 4, 2020 Advanced High-Performance Bus (AHB) Programmable IO Matrix