EZ-PD CCG3PA Datasheet USB Type-C Port Controller General Description EZ-PD CCG3PA is Cypress highly integrated USB Type-C port controller that complies with the latest USB Type-C and PD standards and is targeted for PC power adapters, mobile chargers, car chargers, and power bank applications. In such applications, CCG3PA provides additional functionalities and BOM integration advantages. CCG3PA uses Cypress proprietary M0S8 technology with a 32-bit Arm Cortex-M0 processor, 64-KB flash, a complete Type-C USB-PD transceiver, all termination resistors required for a Type-C port, an integrated feedback control circuitry for voltage (VBUS) regulation and system-level ESD protection. It is available in 24-pin QFN and 16-pin SOIC packages. 32-bit MCU Subsystem Features Arm Cortex-M0 CPU Type-C Support and USB-PD Support 64-KB Flash Supports USB PD3.0 Version 1.1 Spec including Program- 8-KB SRAM mable Power Supply Mode Clocks and Oscillators Configurable resistors R and R P D Integrated oscillator eliminating the need for external clock Supports one USB Type-C port and one Type-A port Power 2x Legacy/Proprietary Charging Blocks 3.0-V to 24.5-V operation (30-V tolerant) Supports QC 4.0, Apple charging 2.4A, AFC, BC 1.2 Integrates all required terminations on DP/DM lines System-Level ESD Protection On CC, VBUS C MON DISCHARGE, DP0, DM0, P2.2, and Integrated Voltage (VBUS) Regulation and Current P2.3 pins Sense Amplifier 8-kV Contact Discharge and 15-kV Air Gap Discharge based Analog regulation of secondary side feedback node (direct on IEC61000-4-2 level 4C feedback or opto coupler) Packages Integrated shunt regulator function for VBUS control 24-pin QFN and 16-pin SOIC Constant current or constant voltage mode Supports extended industrial temperature range (40 C to +105 C) Supports low-side current sensing for constant current control System-Level Fault Protection VBUS to CC Short Protection On-chip OVP, OCP, UVP, and SCP Supports OTP through integrated ADC circuit Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-16951 Rev. *F Revised March 2, 2018EZ-PD CCG3PA Datasheet Logic Block Diagram CCG3PA: Single- Chip Type-C Controller MCU Subsystem I/O Subsystem Integrated Digital Blocks CC ARM 4x TCPWM CORTEX-M0 2x SCB 2 (I C, SPI, UART) GPIOs Flash (64 KB) USB PD Subsystem OCP and OVP Baseband PHY Protection SRAM Low- side Current R , R P D (8 KB) Sense Amplifier Voltage (VBUS) 2x PFET Gate Regulation Drivers System High Voltage Resources 2x VBUS Discharge Regulator 2x 8-bit SAR ADCs 2x Charger Detect Internal Block Diagram VBUS P CTRL VBUS C CTRL VBUS C MON DISCHARGE VBUS IN DISCHARGE OV/UV, R-Div R-Div VDDD HV Reg DISCH 3.3 V Prog VCCD 1.8 V DISCH LDO CC1 BMC PHY CC2 MCU Subsystem DP0 / GPIO Charger Advanced High- Performance Bus Detect0 (AHB) DM0 / GPIO FB Flash SRAM Cortex-M0 DP1 / GPIO (64KB) (8KB) Charger CATH/ Detect1 COMP DM1 / GPIO 2x SCB POR AXRES / GPIO LSCSA 2x ADCs 4x TCPWM (I2C, SPI, UART) GPIO GPIO GND CSP Type-C Connector Ground Rs Document Number: 002-16951 Rev. *F Page 2 of 37 Advanced High- Performance Bus (AHB) Programmable I/O Matrix