EZ-PD CCG4 USB Type-C Port Controller USB Type-C Port Controller General Description EZ-PD CCG4 is a dual USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG4 provides a complete dual USB Type-C and USB-Power Delivery port control solution for notebooks, power adapters and docking stations. It can also be used in dual role and downstream facing port applications. EZ-PD CCG4 uses Cypresss proprietary M0S8 technology with a 32-bit, 48-MHz Arm Cortex -M0 processor with 128 KB flash and integrates two complete Type-C Transceivers including the Type-C termination resistors R and R . P D Integrated dead battery termination for DRP (Power Applications Source/Sink) applications Notebooks Supports two USB Type-C ports Power adapters Integrated VCONN FETs to power EMCA cables Docking stations Integrated fast role swap and extended data messaging Features Low-Power Operation 2.7-V to 5.5-V operation 32-bit MCU Subsystem Independent supply voltage pin for GPIO that allows 1.71-V to 48-MHz Arm Cortex-M0 CPU 5.5-V signaling on the I/Os 128-KB Flash Reset: 1.0 A, Deep Sleep: 2.5 A, Sleep: 2.5 mA 8-KB SRAM System-Level ESD on CC Pins Integrated Digital Blocks 8-kV Contact Discharge and 15-kV Air Gap Discharge based Up to four integrated timers and counters to meet response on IEC61000-4-2 level 4C times required by the USB-PD protocol Four run-time serial communication blocks (SCBs) with Hot Swappable I/Os 2 re-configurable I C, SPI, or UART functionality 2 Port 1 I C pins and CC1, CC2 pins are hot-swappable Clocks and Oscillators Packages Integrated oscillator eliminating the need for external clock 4.0 mm 4.0 mm, 0.5 mm, 24-pin QFN Type-C and USB-PD Support 6.0 mm 6.0 mm, 0.6 mm, 40-pin QFN Integrated USB Power Delivery 3.0 support Supports industrial temperature range (40 C to +85 C) Two integrated USB-PD BMC transceivers 1 2 Integrated UFP (R ) and current sources for DFP (R ) on D P both Type-C ports Notes 1. UFP refers to Power Sink. 2. DFP refers to Power Source. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-98440 Rev. *K Revised June 26, 2018EZ-PD CCG4 Logic Block Diagram CCCCGG44:: SiSinglnglee--CChihip Tp Tyypepe--CC C Coontntrroolllleerr MMCCUU S Subsubsyysstteemm I/I/OO S Subsubsyysstteemm IInntteegrgraatteedd D Diigigittaall Bl Bloocckkss 55 11 4 x4 x T TCCPPWWMM CC CC POPORRTT11 22 COCORRTTEEXX--MM00 4 x4 x S SCCBB 55 CC CC POPORRTT22 22 (I(I CC,, SP SPII,, UA UARTRT)) 48 MH48 MHzz 2x2x V V CCOONN NN PPrrooffileiless a anndd FEFETTss CCoonfnfiigguraurattiioonnss (P(PORORT1T1)) 2x2x V V CCOONN NN 22 x x B Baasseebaband nd MMAACC FlFlaasshh FEFETTss ((128K128KBB)) (P(PORORT2T2)) 22 x x B Baasseebaband nd PHYPHY 66 GPGPIIOOss 33 44 IntInteeggrraatteedd R R aand Rnd R SRASRAMM dd pp ((88KBKB)) 4 x4 x 8 8--bbiitt S SAARR A ADDCC SSeeririaall Wi Wirere De Debubugg 1.1. T Tiimmeerr,, c coouunntteerr,, pul pulssee w wiidtdthh m mooduldulatatiion bon bllocockk 22 2.2. S Seerriiaall c coommmmununicicatatioion bn bllocockk c coonnffiguigurrablable ae ass U UAARRTT,, S SPPII,, or or II CC 3.3. T Teerrmminainattioion rn reessiissttoror d denoenottiinngg a a UUFFPP 4.4. C Cuurrrreenntt s sooururcceess ttoo i indindiccaattee a a DDFFPP 5.5. C Confonfiigurguraattioion cn chanhannelnel 6.6. G Geenerneraall p puurrppoosse e inpinpuutt//ooututpuputt Document Number: 001-98440 Rev. *K Page 2 of 35 AAddvvaancnceedd Hi Higghh--PPeerrffoormarmannccee B Buuss ( (AAHBHB)) PPrrogograrammammablblee I/ I/OO M Maattrriixx