Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comVideo Coprocessor CYV15G0104TRB Independent Clock HOTLink II Serializer and Reclocking Deserializer Features Functional Description Second-generation HOTLink technology The CYV15G0104TRB Independent Clock HOTLink II Serializer and Reclocking Deserializer is a point-to-point or Compliant to SMPTE 292M and SMPTE 259M video point-to-multipoint communications building block enabling standards transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. Single channel video serializer plus single channel video It supports signaling rates in the range of 195 to 1500 Mbps reclocking deserializer per serial link. The transmit and receive channels are 195- to 1500-Mbps serial data signaling rate independent and can operate simultaneously at different Simultaneous operation at different signaling rates rates. The transmit channel accepts 10-bit parallel characters Supports reception of either 1.485 or 1.485/1.001 Gbps data in an Input Register and converts them to serial data. The rate with the same training clock receive channel accepts serial data and converts it to 10-bit parallel characters and presents these characters to an Output Internal phase-locked loops (PLLs) with no external PLL Register. The received serial data can also be reclocked and components retransmitted through the reclocker serial outputs. Figure 1 illustrates typical connections between independent video Supports half-rate and full-rate clocking co-processors and corresponding CYV15G0104TRB chips. Selectable differential PECL-compatible serial inputs The CYV15G0104TRB satisfies the SMPTE 259M and Internal DC-restoration SMPTE 292M compliance as per SMPTE EG34-1999 Patho- logical Test Requirements. Redundant differential PECL-compatible serial outputs No external bias resistors required As a second-generation HOTLink device, the Internal source termination CYV15G0104TRB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining Signaling-rate controlled edge-rates serial-link compatibility (data and BIST) with other HOTLink Synchronous LVTTL parallel interface devices. The transmit (TX) channel of the CYV15G0104TRB HOTLink II device accepts scrambled 10-bit transmission JTAG boundary scan characters. These characters are serialized and output from Built-In Self-Test (BIST) for at-speed link testing dual Positive ECL (PECL) compatible differential trans- mission-line drivers at a bit-rate of either 10- or 20-times the Link quality indicator input reference clock for that channel. Analog signal detect The receive (RX) channel of the CYV15G0104TRB HOTLink Digital signal detect II device accepts a serial bit-stream from one of two selectable Low-power 1.8 W at 3.3 V typical PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers Single 3.3 V supply the timing information necessary for data reconstruction. Thermally enhanced BGA The recovered bit-stream is reclocked and retransmitted through the reclocker serial outputs. Also, the recovered serial Pb-free package option available data is deserialized and presented to the destination host 0.25 BiCMOS technology system. Figure 1. HOTLink II System Connections Reclocked Output 10 10 Independent Independent Channel Channel Serial CYV15G0104TRB CYV15G0104TRB Links Device Device 10 10 Reclocked Output Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-02100 Rev. *G Revised August 18, 2017 Video Coprocessor