CYV15G0203TB-BGXC Infineon

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comVideo Coprocessor CYV15G0203TB Independent Clock Dual HOTLink II Serializer Independent Clock Dual HOTLink II Serializer Features Functional Description Second-generation HOTLink technology The CYV15G0203TB Independent Clock Dual HOTLink II Serializer is a point-to-point or point-to-multipoint Compliant to SMPTE 292M and SMPTE 259M video standards communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and Dual-channel video serializer SMPTE 259M video applications. It supports signaling rates in 195- to 1500-Mbps serial data signaling rate the range of 195 to 1500 Mbps per serial link. The two channels Simultaneous operation at different signaling rates are independent and can simultaneously operate at different Supports half-rate and full-rate clocking rates. Each channel accepts 10-bit parallel characters in an Input Register and converts them to serial data. Figure 1 illustrates Internal phase-locked loops (PLLs) with no external PLL typical connections between independent video co-processors components and corresponding CYV15G0203TB Serializer and CYV15G0204RB Reclocking Deserializer chips. Redundant differential PECL-compatible serial outputs per channel The CYV15G0203TB satisfies the SMPTE-259M and No external bias resistors required SMPTE-292M compliance as per SMPTE EG34-1999 Pathological Test Requirements. Signaling-rate controlled edge-rates Internal source termination As a second-generation HOTLink device, the CYV15G0203TB extends the HOTLink family with enhanced levels of integration Synchronous LVTTL parallel interface and faster data rates, while maintaining serial-link compatibility JTAG boundary scan (data, and BIST) with other HOTLink devices. Each channel of the CYV15G0203TB Dual HOTLink II device accepts scrambled Built-In Self-Test (BIST) for at-speed link testing 10-bit transmission characters. These characters are serialized and output from dual Positive ECL (PECL) compatible differential Low-power 1.4 W 3.3 V typical transmission-line drivers at a bit-rate of either 10- or 20-times the Single 3.3 V supply input reference clock for that channel. Thermally enhanced BGA Each channel contains an independent BIST pattern generator. This BIST hardware allows at-speed testing of the high-speed Pb-free package option available serial data paths in each transmit section of this device, each receive section of a connected HOTLink II device, and across the 0.25 BiCMOS technology interconnecting links. The CYV15G0203TB is ideal for SMPTE applications where different data rates and serial interface standards are necessary for each channel. Some applications include multi-format routers, switchers, format converters, and cameras. Figure 1. HOTLink II System Connections Reclocked Output 10 10 Independent Independent Channel Channel Serial Links CYV15G0203TB CYV15G0204RB Serializer Reclocking Deserializer 10 10 Reclocked Output Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-02105 Rev. *G Revised August 18, 2017 Video Coprocessor