CYWB0124AB-BVXI Infineon

CYWB0124AB CYWB0125AB West Bridge Antioch USB/Mass Storage Peripheral Controller West Bridge Antioch USB/Mass Storage Peripheral Controller Features Applications SLIM architecture, enabling simultaneous and independent Cellular phones data paths between processor and USB, and between USB Portable media players and mass storage Personal digital assistants High speed USB at 480 Mbps USB-2.0 compliant Digital cameras Integrated USB 2.0 transceiver, smart serial interface engine Portable video recorder 16 programmable endpoints Mass storage device support MMC/MMC+/SD/CE-ATA NAND flash: 8 or 16, SLC Full NAND management (ECC, wear leveling) Memory mapped interface to main processor DMA slave support Supports Microsoft media transfer protocol (MTP) with optimized data throughput Ultra low power, 1.8 V core operation Low power modes Small footprint, 6 6 mm VFBGA, and less than 4 4 mm WLCSP Selectable clock input frequencies 19.2 MHz, 24 MHz, 26 MHz, and 48 MHz Logic Block Diagram West Bridge Antioch Control 8051 Registers MCU P U TM SLIM Mass Storage Interface SD/MMC+/CE-ATA NAND S Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-07978 Rev. *O Revised December 1, 2017 Processor Interface High-Speed USB 2.0 XCVRCYWB0124AB CYWB0125AB Contents Functional Overview ........................................................3 AC Characteristics ......................................................... 15 SLIM Architecture ....................................................3 USB Transceiver ....................................................... 15 Turbo-MTP Support .....................................................3 P-Port Interface ......................................................... 15 8051 Microprocessor ...................................................3 SD/MMC Parameters ................................................ 22 Configuration and Status Registers .............................3 Reset and Standby Timing Parameters .................... 23 Processor Interface (P-port) ........................................3 Ordering Information ...................................................... 24 USB Interface (U-Port) ................................................3 Ordering Code Definitions ......................................... 24 Mass Storage Support (S-Port) ...................................3 Package Diagrams .......................................................... 25 Clocking .......................................................................4 Acronyms ........................................................................27 Power Domains ...........................................................5 Document Conventions ................................................. 27 Power Modes ..............................................................5 Units of Measure ....................................................... 27 Antioch in WLCSP .......................................................6 Document History Page ................................................. 28 Absolute Maximum Ratings ..........................................12 Sales, Solutions, and Legal Information ...................... 31 Operating Conditions .....................................................12 Worldwide Sales and Design Support ....................... 31 DC Characteristics .........................................................12 Products ....................................................................31 USB Transceiver .......................................................14 PSoCSolutions .......................................................31 Capacitance ....................................................................14 Cypress Developer Community ................................. 31 AC Test Loads and Waveforms .....................................14 Technical Support ..................................................... 31 Document Number: 001-07978 Rev. *O Page 2 of 31