IPB017N10N5LF MOSFET TM D-PAK 7pin OptiMOS 5 Linear FET , 100 V Features Ideal for hot-swap and e-fuse applications tab Very low on-resistance RDS(on) Wide safe operating area SOA N-channel, normal level 1 100% avalanche tested Pb-free plating RoHS compliant 7 1) Qualified according to JEDEC for target applications Halogen-free according to IEC61249-2-21 Drain Table 1 Key Performance Parameters Pin 4, tab Parameter Value Unit V 100 V DS Gate Pin 1 RDS(on),max 1.7 m Source Pin 2,3,5,6,7 I (silicon limited) 314 A D I (package limited) 180 A D I (V =56 V, t =10 pulse DS p 10.2 A ms) Type / Ordering Code Package Marking Related Links IPB017N10N5LF PG-TO 263-7 017N10LF - 1) J-STD20 and JESD22 Final Data Sheet 1 Rev. 2.1, 2017-02-16TM OptiMOS 5 Linear FET , 100 V IPB017N10N5LF Table of Contents Description . 1 Maximum ratings 3 Thermal characteristics 3 Electrical characteristics . 4 Electrical characteristics diagrams . 6 Package Outlines . 10 Revision History 11 Trademarks . 11 Disclaimer 11 Final Data Sheet 2 Rev. 2.1, 2017-02-16