97370 IRLS4030PbF IRLSL4030PbF Applications HEXFET Power MOSFET DC Motor Drive D High Efficiency Synchronous Rectification in SMPS V 100V DSS Uninterruptible Power Supply R typ. High Speed Power Switching 3.4m DS(on) Hard Switched and High Frequency Circuits G max. 4.3m I S 180A D Benefits Optimized for Logic Level Drive Very Low R at 4.5V V DS(ON) GS Superior R*Q at 4.5V V GS Improved Gate, Avalanche and Dynamic dV/dt Ruggedness S S Fully Characterized Capacitance and Avalanche D D G G SOA 2 D Pak TO-262 Enhanced body diode dV/dt and dI/dt Capability IRLS4030PbF IRLSL4030bF Lead-Free GD S Gate Drain Source Absolute Maximum Ratings Symbol Parameter Max. Units I T = 25C Continuous Drain Current, V 10V 180 D C GS I T = 100C Continuous Drain Current, V 10V 130 A D C GS I 730 DM Pulsed Drain Current P T = 25C Maximum Power Dissipation 370 W D C 2.5 Linear Derating Factor W/C V Gate-to-Source Voltage 16 V GS 21 dv/dt Peak Diode Recovery V/ns T Operating Junction and -55 to + 175 C J T STG Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case) Avalanche Characteristics Single Pulse Avalanche Energy E 305 mJ AS (Thermally limited) Avalanche Current I See Fig. 14, 15, 22a, 22b A AR Repetitive Avalanche Energy E mJ AR Thermal Resistance Symbol Parameter Typ. Max. Units R Junction-to-Case 0.40 C/W JC R 40 JA Junction-to-Ambient (PCB Mount) www.irf.com 1 02/12/09 Static T = 25C (unless otherwise specified) J Symbol Parameter Min. Typ. Max. Units Conditions V Drain-to-Source Breakdown Voltage 100 V V = 0V, I = 250A (BR)DSS GS D V / T Breakdown Voltage Temp. Coefficient 0.10 V/C Reference to 25C, I = 5mA (BR)DSS J D R Static Drain-to-Source On-Resistance 3.4 4.3 V = 10V, I = 110A DS(on) m GS D 3.6 4.5 V = 4.5V, I = 92A GS D V Gate Threshold Voltage 1.0 2.5 V V = V , I = 250A GS(th) DS GS D I Drain-to-Source Leakage Current 20 V = 100V, V = 0V DSS DS GS A 250 V = 100V, V = 0V, T = 125C DS GS J I Gate-to-Source Forward Leakage 100 V = 16V GSS GS nA Gate-to-Source Reverse Leakage -100 V = -16V GS R Internal Gate Resistance 2.1 G(int) Dynamic T = 25C (unless otherwise specified) J Symbol Parameter Min. Typ. Max. Units Conditions gfs Forward Transconductance 320 S V = 25V, I = 110A DS D Q Total Gate Charge 87 130 I = 110A g D Q Gate-to-Source Charge 27 V = 50V gs DS nC Q Gate-to-Drain Mille) Charge 45 V = 4.5V gd GS Q Total Gate Charge Sync. (Q - Q ) 42 I = 110A, V =0V, V = 4.5V sync g gd D DS GS t Turn-On Delay Time 74 V = 65V d(on) DD t Rise Time 330 I = 110A r D ns t Turn-Off Delay Time 110 R = 2.7 d(off) G t Fall Time 170 V = 4.5V f GS C Input Capacitance 11360 V = 0V iss GS C Output Capacitance 670 V = 50V oss DS C Reverse Transfer Capacitance 290 pF = 1.0MHz rss C eff. (ER) 760 V = 0V, V = 0V to 80V oss Effective Output Capacitance (Energy Related) GS DS C eff. (TR) 1140 V = 0V, V = 0V to 80V oss Effective Output Capacitance (Time Related) GS DS Diode Characteristics Symbol Parameter Min. Typ. Max. Units Conditions I D Continuous Source Current MOSFET symbol S 180 (Body Diode) showing the A G I Pulsed Source Current integral reverse SM 730 S (Body Diode) p-n junction diode. V Diode Forward Voltage 1.3 V T = 25C, I = 110A, V = 0V SD J S GS t Reverse Recovery Time 50 T = 25C V = 85V, rr J R ns T = 125C I = 110A 60 J F di/dt = 100A/s Q T = 25C Reverse Recovery Charge 88 rr J nC T = 125C 130 J I Reverse Recovery Current 3.3 A T = 25C RRM J t Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) on Repetitive rating pulse width limited by max. junction C eff. (TR) is a fixed capacitance that gives the same charging time oss temperature. as C while V is rising from 0 to 80% V . oss DS DSS Limited by T , starting T = 25C, L = 0.05mH Jmax J C eff. (ER) is a fixed capacitance that gives the same energy as oss R = 25 , I = 110A, V =10V. Part not recommended for use G AS GS C while V is rising from 0 to 80% V . oss DS DSS above this value . When mounted on 1 square PCB (FR-4 or G-10 Material). For I 110A, di/dt 1330A/s, V V , T 175C. SD DD (BR)DSS J recommended footprint and soldering techniquea refer to applocation Pulse width 400s duty cycle 2%. note AN- 994 echniques refer to application note AN-994. JC 2 www.irf.com