S34ML08G101TFI003 Infineon

S34ML08G1 8 Gb, 1-bit ECC, x8 I/O, 3 V, V CC NAND Flash Memory for Embedded General Description The Cypress S34ML08G1 8-Gb NAND is offered in 3.3 V with x8 I/O interface. This document contains information for the CC S34ML08G1 device, which is a dual-die stack of two S34ML04G1 die. For detailed specifications, please refer to the discrete die datasheet: S34ML04G1. Distinctive Characteristics Density Security 8 Gb (4 Gb 2) One Time Programmable (OTP) area Hardware program/erase disabled during power transition Architecture (For each 4 Gb device) Input / Output Bus Width: 8-bits Additional Features Page Size: (2048 + 64) bytes; 64 bytes is spare area Supports Multiplane Program and Erase commands Block Size: 64 Pages or (128k + 4k) bytes Supports Copy Back Program Plane Size Supports Multiplane Copy Back Program 2048 Blocks per Plane or (256M + 8M) bytes Supports Read Cache Device Size Electronic Signature 2 Planes per Device or 512 Mbyte Manufacturer ID: 01h NAND Flash Interface Operating Temperature Open NAND Flash Interface (ONFI) 1.0 compliant Industrial: 40 C to 85 C Address, Data and Commands multiplexed Automotive: 40 C to 105 C Supply Voltage 3.3 V device: Vcc = 2.7 V ~ 3.6 V Performance Page Read / Program Reliability Random access: 25 s (Max) 100,000 Program / Erase cycles (Typ) (with 1 bit / 512 + 16 byte ECC) Sequential access: 25 ns (Min) 10 Year Data retention (Typ) Program time / Multiplane Program time: 200 s (Typ) Blocks zero and one are valid and will be valid for at least Block Erase / Multiplane Erase (S34ML04G1) 1000 program-erase cycles with ECC Block Erase time: 3.5 ms (Typ) Package Options Lead Free and Low Halogen 48-Pin TSOP 12 20 1.2 mm 63-Ball BGA 9 11 1 mm Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00483 Rev. *H Revised January 12, 2016S34ML08G1 Contents 1. Connection Diagram.................................................... 3 8. Electrical Characteristics........................................... 13 8.1 Valid Blocks .................................................................. 13 2. Pin Description............................................................. 5 8.2 DC Characteristics........................................................ 14 3. Block Diagrams............................................................ 6 8.3 Pin Capacitance............................................................ 14 8.4 Power Consumptions and Pin Capacitance for Allowed 4. Addressing ................................................................... 8 Stacking Configurations................................................ 14 5. Read Status Enhanced ................................................ 9 9. Physical Interface ....................................................... 15 6. Extended Read Status ................................................. 9 9.1 Physical Diagram.......................................................... 15 7. Read ID........................................................................ 10 10. Ordering Information.................................................. 17 7.1 Read Parameter Page ................................................. 11 11. Appendix A Errata.................................................. 18 12. Revision History.......................................................... 19 Document Number: 002-00483 Rev. *H Page 2 of 21