Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comS27KL0641/S27KS0641 S70KL1281/S70KS1281 3.0 V/1.8 V, 64 Mb (8 MB)/128 Mb (16 MB), HyperRAM Self-Refresh DRAM Distinctive Characteristics Up to 333 MBps HyperRAM Low Signal Count Interface Double-Data Rate (DDR) - two data transfers per clock 3.0 V I/O, 11 bus signals Single ended clock (CK) 166 MHz clock rate (333 MBps) at 1.8 V V CC 1.8 V I/O, 12 bus signals 100 MHz clock rate (200 MBps) at 3.0 V V CC Differential clock (CK, CK ) Sequential burst transactions Chip Select (CS ) Configurable Burst Characteristics 8-bit data bus (DQ 7:0 ) Wrapped burst lengths: 16 bytes (8 clocks) Read-Write Data Strobe (RWDS) 32 bytes (16 clocks) Bidirectional Data Strobe / Mask 64 bytes (32 clocks) Output at the start of all transactions to indicate refresh la- tency 128 bytes (64 clocks) Output during read transactions as Read Data Strobe Linear burst Input during write transactions as Write Data Mask Hybrid option - one wrapped burst followed by linear burst Wrapped or linear burst type selected in each transaction RWDS DCARS Timing Configurable output drive strength During read transactions RWDS is offset by a second clock, phase shifted from CK Low Power Modes The Phase Shifted Clock is used to move the RWDS transi- Deep Power Down tion edge within the read data eye Package High Performance 24-ball FBGA Performance Summary Read Transaction Timings Maximum Clock Rate at 1.8 V V /V Q 166 MHz CC CC Maximum Clock Rate at 3.0 V V /V Q 100 MHz CC CC Maximum Access Time, (t at 166 MHz) 36 ns ACC Maximum CS Access Time to first word at 56 ns 166 MHz (excluding refresh latency) Maximum Current Consumption 64 MB 128 MB Burst Read or Write (linear burst at 166 MHz, 1.8 V) 60 mA 72 mA Power On Reset 50 mA 100 mA Standby (CS = HIGH, 3.0 V, 105 C) 300 A 600 A Deep Power Down (CS = HIGH, 3.0 V, 105 C) 40 A N/A Standby (CS = HIGH, 1.8 V, 105 C) 300 A 600 A Deep Power Down (CS = HIGH, 1.8 V, 105 C) 20 A N/A Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-97964 Rev. *M Revised July 19, 2019