Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comS70KL1283/S70KS1283 3.0 V/1.8 V, 128 Mb (16 MB), Octal (xSPI) Interface HyperRAM (Self-Refresh DRAM) S70KL1283/S70KS1283, 3.0 V/1.8 V, 64 Mb (8 MB), HyperRAM Self-Refresh DRAM Configurable Burst Characteristics Features Linear burst Interface Wrapped burst lengths: 16 bytes (8 clocks) xSPI (Octal) Interface 32 bytes (16 clocks) 1.8 V / 3.0 V Interface support 64 bytes (32 clocks) Single ended clock (CK) - 11 bus signals 128 bytes (64 clocks) Optional Differential clock (CK, CK ) - 12 bus signals Hybrid option - one wrapped burst followed by linear burst on 64 Mb. Linear Burst across die boundary is not supported. Chip Select (CS ) Configurable output drive strength 8-bit data bus (DQ 7:0 ) 1 Power Modes Hardware reset (RESET ) Hybrid Sleep Mode Bidirectional Read-Write Data Strobe (RWDS) Deep Power Down Output at the start of all transactions to indicate refresh Array Refresh latency Output during read transactions as Read Data Strobe Partial Memory Array (1/8, 1/4, 1/2, and so on) Input during write transactions as Write Data Mask Full Optional DDR Center-Aligned Read Strobe (DCARS) Package During read transactions RWDS is offset by a second clock, 24-ball FBGA phase shifted from CK Operating Temperature Range The Phase Shifted Clock is used to move the RWDS Industrial (I): 40 C to +85 C transition edge within the read data eye Industrial Plus (V): 40 C to +105 C Performance, Power, and Packages Automotive, AEC-Q100 Grade 3: 40 C to +85 C Automotive, AEC-Q100 Grade 2: 40 C to +105C 200-MHz maximum clock rate Technology DDR - transfers data on both edges of the clock 38-nm DRAM Data throughput up to 400 MBps (3,200 Mbps) Note 1. 128-Mb HyperRAM is a stacked-die chip using two 64-Mb dice. Only one die, at a time, can be programmed to enter Hybrid Sleep Mode mode or Deep Power Down mode. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-29418 Rev .** Revised February 07, 2020