Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comSL811HS Embedded USB Host/Slave Controller Embedded USB Host/Slave Controller Features Functional Description First USB Host/Slave controller for embedded systems in the The SL811HS is an Embedded USB Host/Slave Controller market with a standard microprocessor bus interface capable of communicating in either full speed or low speed. The SL811HS interfaces to devices such as microprocessors, micro- Supports both full speed (12 Mbps) and low speed (1.5 Mbps) controllers, DSPs, or directly to a variety of buses such as ISA, USB transfer in both master and slave modes PCMCIA, and others. The SL811HS USB Host Controller conforms to USB Specification 1.1. Conforms to USB Specification 1.1 for full- and low speed The SL811HS incorporates USB Serial Interface functionality Operates as a single USB host or slave under software control along with internal full or low speed transceivers. The SL811HS Automatic detection of either low- or full-speed devices supports and operates in USB full speed mode at 12 Mbps, or in low-speed mode at 1.5 Mbps. When in host mode, the SL811HS 8-bit bidirectional data, port I/O (DMA supported in slave mode) is the master and controls the USB bus and the devices that are connected to it. In peripheral mode, otherwise known as a slave On-chip SIE and USB transceivers device, the SL811HS operates as a variety of full- or low-speed On-chip single root HUB support devices. 256-byte internal SRAM buffer The SL811HS data port and microprocessor interface provide an 8-bit data path I/O or DMA bidirectional, with interrupt support to Ping-pong buffers for improved performance allow easy interface to standard microprocessors or microcontrollers such as Motorola or Intel CPUs and many Operates from 12 or 48 MHz crystal or oscillator (built-in DPLL) others. The SL811HS has 256 bytes of internal RAM, which is 5 V-tolerant interface used for control registers and data buffers. Suspend/resume, wake up, and low-power modes are The available Pb-free package is a 48-pin (SL811HST-AXC) supported package. All packages operate at 3.3 VDC. The I/O interface logic is 5 V-tolerant. Auto-generation of SOF and CRC5/16 Auto-address increment mode, saves memory READ/WRITE cycles Development kit including source code drivers is available 3.3-V power source, 0.35 micron CMOS technology Available in 48-pin TQFP package Logic Block Diagram Master/Slave INTERRUPT Controller INTR CONTROLLER 256 Byte RAM D SERIAL USB + BUFFERS INTERFACE nDRQ Root HUB D- & DMA ENGINE CONTROL Interface XCVRS REGISTERS nDACK nWR nRD PROCESSOR nCS CLOCK INTERFACE nRST GENERATOR D0-7 X1 X2 Errata: For information on silicon errata, see Errata on page 33. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-08008 Rev. *J Revised August 1, 2017