ISPGDX160VA-7B208 Lattice

ispGDX 160V/VA Device Datasheet June 2010 Select Devices Discontinued Product Change Notification (PCN) 09-10 has been issued to discontinue select devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN ispGDX160V-5B272 Discontinued PCN 09-10 ispGDX160V-7B272 ispGDX160V-5B208 ispGDX160V-7B208 ispGDX160V ispGDX160V-5Q208 Active / Orderable ispGDX160V-7Q208 ispGDX160V-7Q208I ispGDX160VA-3B272 ispGDX160VA-5B272 ispGDX160VA-7B272 Discontinued PCN 09-10 ispGDX160VA-5B272I ispGDX160VA-7B272I ispGDX160VA-9B272I ispGDX160VA-3Q208 ispGDX160VA-5Q208 ispGDX160VA-7Q208 ispGDX160VA-5Q208I ispGDX160VA-7Q208I ispGDX160VA-9Q208I ispGDX160VA ispGDX160VA-3B208 ispGDX160VA-3BN208 ispGDX160VA-5B208 Active / Orderable ispGDX160VA-5BN208 ispGDX160VA-7B208 ispGDX160VA-7BN208 ispGDX160VA-5B208I ispGDX160VA-5BN208I ispGDX160VA-7B208I ispGDX160VA-7BN208I ispGDX160VA-9B208I ispGDX160VA-9BN208I 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347 Internet: I/O Pins C ispGDX 160V/VA In-System Programmable 3.3V Generic Digital Crosspoint Features Functional Block Diagram IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY ISP I/O Pins D Control Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement Any Input to Any Output Routing Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation Space-Saving PQFP and BGA Packaging Global Routing Dedicated IEEE 1149.1-Compliant Boundary Scan I/O I/O Pool Cells Cells Test (GRP) 2 HIGH PERFORMANCE E CMOS TECHNOLOGY 3.3V Core Power Supply 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay* 250MHz Maximum Clock Frequency* TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels (Individually Programmable)* Low-Power: 16.5mA Quiescent Icc* Boundary 24mA I Drive with Programmable Slew Rate Scan I/O Pins B OL Control Control Option PCI Compatible Drive Capability* Schmitt Trigger Inputs for Noise Immunity Electrically Erasable and Reprogrammable Description 2 Non-Volatile E CMOS Technology The ispGDXV/VA architecture provides a family of fast, ispGDXV OFFERS THE FOLLOWING ADVANTAGES flexible programmable devices to address a variety of 3.3V In-System Programmable Using Boundary Scan system-level digital signal routing and interface require- Test Access Port (TAP) ments including: Change Interconnects in Seconds FLEXIBLE ARCHITECTURE Multi-Port Multiprocessor Interfaces Combinatorial/Latched/Registered Inputs or Outputs Individual I/O Tri-state Control with Polarity Control Wide Data and Address Bus Multiplexing Dedicated Clock/Clock Enable Input Pins (four) or (e.g. 16:1 High-Speed Bus MUX) Programmable Clocks/Clock Enables from I/O Pins Programmable Control Signal Routing (40) (e.g. Interrupts, DMAREQs, etc.) Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns) Programmable Wide-MUX Cascade Feature Board-Level PCB Signal Routing for Prototyping or Supports up to 16:1 MUX Programmable Bus Interfaces Programmable Pull-ups, Bus Hold Latch and Open Drain on I/O Pins The devices feature fast operation, with input-to-output Outputs Tri-state During Power-up (Live Insertion Friendly) signal delays (Tpd) of 3.5ns and clock-to-output delays of 3.5ns. LEAD-FREE PACKAGE OPTIONS The architecture of the devices consists of a series of * VA Version Only programmable I/O cells interconnected by a Global Rout- ing Pool (GRP). All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the required I/O outputs. I/O pin inputs are defined as four sets (A,B,C,D) which have access to the four MUX inputs Copyright 2004 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2004 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556