I/O Pins C ispGDX 240VA In-System Programmable 3.3V Generic Digital Crosspoint Features Functional Block Diagram IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY ISP I/O Pins D Control 240 I/O, Any Input to Any Output Routing Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation Space-Saving Fine Pitch BGA Packaging Global Routing Dedicated IEEE 1149.1-Compliant Boundary Scan I/O I/O Pool Cells Cells Test (GRP) 2 HIGH PERFORMANCE E CMOS TECHNOLOGY 3.3V Core Power Supply 4.5ns Input-to-Output/4.0ns Clock-to-Output Delay 200MHz Maximum Clock Frequency TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels (Individually Programmable) Low-Power: 20.0mA Quiescent Icc Boundary 24mA I Drive with Programmable Slew Rate Scan I/O Pins B OL Control Control Option PCI Compatible Drive Capability Schmitt Trigger Inputs for Noise Immunity Electrically Erasable and Reprogrammable Description 2 Non-Volatile E CMOS Technology The ispGDXVA architecture provides a family of fast, ispGDXVA OFFERS THE FOLLOWING ADVANTAGES flexible programmable devices to address a variety of 3.3V In-System Programmable Using Boundary Scan system-level digital signal routing and interface require- Test Access Port (TAP) ments including: Change Interconnects in Seconds FLEXIBLE ARCHITECTURE Multi-Port Multiprocessor Interfaces Combinatorial/Latched/Registered Inputs or Outputs Individual I/O Tri-state Control with Polarity Control Wide Data and Address Bus Multiplexing Dedicated Clock/Clock Enable Input Pins (four) or (e.g. 16:1 High-Speed Bus MUX) Programmable Clocks/Clock Enables from I/O Pins (60) Programmable Control Signal Routing Single Level 4:1 Dynamic Path Selection (Tpd = 4.5ns) (e.g. Interrupts, DMAREQs, etc.) Programmable Wide-MUX Cascade Feature Supports up to 16:1 MUX Board-Level PCB Signal Routing for Prototyping or Programmable Pull-ups, Bus Hold Latch and Open Programmable Bus Interfaces Drain on I/O Pins Outputs Tri-state During Power-up (Live Insertion The ispGDX240VA device features fast operation, with Friendly) input-to-output signal delays (Tpd) of 4.5ns and clock-to- LEAD-FREE PACKAGE OPTIONS output delays of 4.0ns. The architecture of the devices consists of a series of programmable I/O cells interconnected by a Global Rout- ing Pool (GRP). All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the required I/O outputs. I/O pin inputs are defined as four sets (A,B,C,D) which have access to the four MUX inputs Copyright 2004 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2004 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Specifications ispGDX240VA Description (Continued) found in each I/O cell. Each output has individual, pro- In addition, there are no pin-to-pin routing constraints for grammable I/O tri-state control (OE), output latch clock 1:1 or 1:n signal routing. That is, any I/O pin configured (CLK), clock enable (CLKEN), and two multiplexer con- as an input can drive one or more I/O pins configured as trol (MUX0 and MUX1) inputs. Polarity for these signals outputs. is programmable for each I/O cell. The MUX0 and MUX1 The device pins also have the ability to set outputs to inputs control a fast 4:1 MUX, allowing dynamic selection fixed HIGH or LOW logic levels (Jumper or DIP Switch of up to four signal sources for a given output. A wider mode). Device outputs are specified for 24mA sink and 16:1 MUX can be implemented with the MUX expander 12mA source current (at JEDEC LVTTL levels) and can feature of each I/O and a propagation delay increase of be tied together in parallel for greater drive. On the 2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs ispGDXVA, each I/O pin is individually programmable for can be driven directly from selected sets of I/O pins. 3.3V or 2.5V output levels as described later. Program- Optional dedicated clock input pins give minimum clock- mable output slew rate control can be defined to-output delays. CLK and CLKEN share the same set of independently for each I/O pin to reduce overall ground I/O pins. CLKEN disables the register clock when bounce and switching noise. CLKEN = 0. All I/O pins are equipped with IEEE1149.1-compliant Through in-system programming, connections between Boundary Scan Test circuitry for enhanced testability. In I/O pins and architectural features (latched or registered addition, in-system programming is supported through inputs or outputs, output enable control, etc.) can be the Test Access Port via a special set of private com- defined. In keeping with its data path application focus, mands. the ispGDXVA devices contain no programmable logic arrays. All input pins include Schmitt trigger buffers for The ispGDXVA I/Os are designed to withstand live noise immunity. These connections are programmed insertion system environments. The I/O buffers are 2 into the device using non-volatile E CMOS technology. disabled during power-up and power-down cycles. When Non-volatile technology means the device configuration designing for live insertion, absolute maximum rating is saved even when the power is removed from the conditions for the Vcc and I/O pins must still be met. device. Table 1. ispGDXVA Family Members ispGDXV/VA Device ispGDX80VA ispGDX160V/VA ispGDX240VA I/O Pins 80 160 240 I/O-OE Inputs* 20 40 60 I/O-CLK / CLKEN Inputs* 20 40 60 I/O-MUXsel1 Inputs* 20 40 60 I/O-MUXsel2 Inputs* 20 40 60 Dedicated Clock Pins** 2 4 4 EPEN 1 1 1 TOE 1 1 1 BSCAN Interface 4 4 4 1 1 1 RESET Pin Count/Package 100-Pin TQFP 208-Pin PQFP 388-Ball fpBGA 208-Ball fpBGA 272-Ball BGA * The CLK/CLK EN, OE, MUX0 and MUX1 terminals on each I/O cell can each be assigned to 25% of the I/Os. ** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and CLKEN3 respectively in all devices. 2