M21350-15/M21355-15 3G/HD/SD-SDI Multi-rate Video Quad Reclocker Rev V6 Quad 4:1 Mux (M21350) Applications Common reference clock for all channels 3G/HD/SD-SDI Video Switchers Input equalization and output de-emphasis for 40 of FR4 trace 3G/HD/SD-SDI Video Routers 135 mW power consumption per channel (1.2 V operation) 3G/HD/SD-SDI Video Distribution Amplifiers Integrated regulators for multi-voltage operation (1.2 V - 3.3 V) DVB-ASI Equipment Electrically independent input, output, and core supply rails Recovered serial clock output option Features Output enable/disable and configurable auto or manual bypass mode Independent, quad channel, multi-rate reclocker Automatic and manual modes for rate indication and selection SMPTE 259M-C, 292, 424M, and DVB ASI Compliant Loss of Lock (LOL), Loss of Signal (LOS) and data rate indication Greater than 0.6 UI Input Jitter Tolerance Two-wire and four-wire serial control interfaces Integrated 50 input termination Industrial operating temperature range (-40 C to +85 C) 16x4 Input Crosspoint (M21355) The M21350 and M21355 are quad serial digital video reclockers with integrated trace equalization, and automatic rate detect (ARD) circuitry. The M21350 has a 4:1 mux on the input of each reclocker channel whereas the M21355 has a common 16x4 crosspoint switch at the input to all four channels. It operates at SDI data rates ranging from 270 Mbps to 2970 Mbps and is compliant to SMPTE 424M, SMPTE292, and SMPTE 259M-C. At 270 Mbps, it also supports DVB-ASI. The M21350 and M21355 have an input jitter tolerance (IJT) of greater than 0.6 unit intervals (UI) and can provide retimed serial data outputs with very low alignment jitter. The quad reclockers require a single, external, 27 MHz crystal, which is used as the reference clock for all four channels. The devices also include per lane analog input equalization for up to 40 of FR4 trace and two connectors in addition to output de-emphasis. These devices feature integrated supply regulators, allowing it to be powered from 1.2 V, 1.8 V, 2.5 V, or 3.3 V supply voltages. When operating at 1.2 V, it consumes only 135 mW per channel at 3G-SDI. Furthermore, the power rails for the core, input, and output circuitry are electrically independent and as such may be connected to different voltage rails on the board. This feature enables the M21350/M21355 to be DC coupled to any upstream or downstream device regardless of its input/output voltage level. Each of the M21350 s quad input MUXes allow any of the four inputs to be switched to the respective reclocker channel. The M21355 s 16x4 input crosspoint allows any of the 16 inputs to be routed to any of the four integrated reclockers. The devices can be configured by setting the internal registers though standard two-wire and four-wire interfaces. Limited configuration is also possible through hardware pin settings. The M21350 and M21355 are offered in a green and RoHS-compliant, 10 mm x 10 mm, 72-pin QFN packaging. M21350/M21355 Block Diagram SDI0P IE SDI0N 50 Buffer SDO0P SDI1P Reclocker 0 IE W/ DE SDO0N SDI1N 50 Buffer SDO1P Reclocker 1 16x4 W/ DE SDO1N XPT or Quad 50 Buffer SDO2P 4:1 Mux Reclocker 2 W/ DE SDO2N SDI14P IE 50 Buffer SDO3/SCLKP Reclocker 3 SDI14N W/ DE SDO3/SCLKN SDI15P IE SDI15N 1 M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. Visit www.macom.com for additional data sheets and product information. For further information and support please visit: M21350-15/M21355-15 3G/HD/SD-SDI Multi-rate Video Quad Reclocker Rev V6 Ordering Information Part Number Package Operating Temperature M21350G-15* 10 x 10 mm, 72-pin QFN package -40 C to 85 C M21355G-15* 10 x 10 mm, 72-pin QFN package -40 C to 85 C * The letter G designator after the part number indicates that the device is RoHS compliant. The RoHS compliant devices are backwards compatible with 225 C reflow profiles. Revision History Revision Level Date Description V6 Release December 2015 Updated package drawing, Figure 3-12 and Figure 3-13. Package effective as of August 2014. V5 Release June 2015 Updated logos and page layout. No content changes. I (V4) Release June 2012 Section 4.6.2: Revised 4 wire interface. Revised register address 0Bh default to 08h. H (V3) Release December 2011 Figure 3-1: Typo fixed in Pin 66, Pin 11 changed from DIN2P to SDI2P, Pin 12 changed from DIN2N to SDI2N. Table 4-2: Function description for pins MF4 and MF5 modified to make low equivalent to floating. Table 1-8: Added 2-state input to VIH and VIL. Section 4.7.1: Renamed SDOA to SDO0. Section 4.9.2: Inserted a note to add a 10 k pull to AV . DDIO 2 M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. Visit www.macom.com for additional data sheets and product information. For further information and support please visit: