Short Form Data Sheet April 2012 DS31408 8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock General Description Features Eight Input Clocks The DS31408 is a flexible, high-performance timing IC for diverse frequency conversion and frequency Differential or CMOS/TTL Format synthesis applications. On each of its eight input clocks Any Frequency from 2kHz to 750MHz and fourteen output clocks, the device can accept or Fractional Scaling for 64B/66B and FEC Scaling (e.g., 64/66, 237/255, 238/255) or Any generate nearly any frequency between 2kHz and Other Downscaling Requirement 750MHz. The device offers two independent DPLLs to Continuous Input Clock Quality Monitoring serve two independent clock-generation paths. The Two High-Performance DPLLs input clocks are divided down, fractionally scaled as needed, and continuously monitored for activity and Hitless Reference Switching on Loss of Input frequency accuracy. The best input clock is selected, Automatic or Manual Phase Build-Out manually or automatically, as the reference clock for Holdover on Loss of All Inputs each of the two flexible, high-performance digital PLLs. Programmable Bandwidth, 0.5mHz to 400Hz Each DPLL lock to the selected reference and provides Seven Digital Frequency Synthesizers programmable bandwidth, very high resolution holdover Each Can Slave to Either DPLL capability, and truly hitless switching between input Produce Any 2kHz Multiple Up to 77.76MHz clocks. The digital PLLs are followed by a clock Three Output APLLs synthesis subsystem that has seven fully programmable Output Frequencies to 750MHz digital frequency synthesis blocks, three high-speed High Resolution Fractional Scaling for FEC and low-jitter APLLs, and 14 output clocks, each with its own 64B/66B (e.g., 255/237, 255/238, 66/64) or Any 32-bit divider and phase adjustment. The APLLs Other Scaling Requirement provide fractional scaling and output jitter less than 1ps Less than 1ps RMS Output Jitter RMS. For telecom systems, the DS31408 has all Simultaneously Produce Three Low-Jitter Rates required features and functions to serve as a central from the Same Reference (e.g., 622.08MHz for timing function or as a line card timing IC. SONET, 255/237*622.08MHz for OTU2, and 156.25MHz for 10GE) In addition the DS31408 has an embedded IEEE 1588 14 Output Clocks in Seven Groups clock that can be steered by system software to follow a Nearly Any Frequency from < 1Hz to 750MHz time master elsewhere in the system or elsewhere in Each Group Slaves to a DFS Clock, Any APLL the network. This clock has all necessary features to be Clock, or Any Input Clock (Divided and Scaled) the central time clock in a 1588 ordinary clock, Each Has a Differential Output (3 CML, 4 LVDS/ boundary clock or transparent clock. LVPECL) and Separate CMOS/TTL Output 32-Bit Frequency Divider Per Output Applications IEEE 1588 Clock Features Frequency Conversion and IEEE1588 Time/Frequency -8 Steerable by Software with 2 ns Time Resolution Applications in a Wide Variety of Equipment Types and -32 Telecom Line Cards or Timing Cards with Any Mix of 2 ns Frequency Resolution SONET/SDH, Synchronous Ethernet and/or OTN 4ns Input Timestamp Accuracy and Output Edge Ports in WAN Equipment Including MSPPs, Ethernet Placement Accuracy Switches, Routers, DSLAMs, and Base Stations Programmable Clock and Time-Alignment I/O to Synchronize All 1588 Devices in Large Systems Ordering Information Supports 1588 OC, BC, and TC Architectures PART TEMP RANGE PIN-PACKAGE General Features Suitable Line Card IC or Timing Card IC for Stratum DS31408GN -40 C to +85 C 256 CSBGA 2/3E/3/4E/4, SMC, SEC/EEC, or SSU DS31408GN+ -40 C to +85 C 256 CSBGA Accepts and Produces Nearly Any Frequency from +Denotes a lead(Pb)-free/RoHS-compliant package. 1Hz Up to 750MHz SPI is a trademark of Motorola, Inc. Internal Compensation for Local Oscillator Frequency Error SPI Processor Interface 1.8V Operation with 3.3V I/O (5V Tolerant) 1 Short Form Data Sheet DS31408 Application Examples Typical Timing Card Application Example activity and frequency clock/data recovery, monitoring, select highest priority create derived DS1 or E1/2048kHz equalizer, framer, clock locked to selected clock valid input for each DPLL extract SSMs Timing Card (1 of 2) from BITS/SSU Backplane BITS Rx DS31408 DS1, E1 or 2048 kHz N to BITS/SSU BITS APLL and DPLL1 <0> Tx divider Monitor, Divider, Selector APLL, TCXO or processor DPLL2 divider and OCXO fanout N typically 19.44MHz, Stratum 2, 3E or 3: 25MHz or 8kHz, jitter/wander filtering, point-to-point hitless switching, or multidrop buses N phase adjust, Timing Card (2 of 2) holdover <0> Identical to Timing Card 1 N <1> Line Card (1 of N) Line Card <1> Timing IC from port SERDES <1> to port SERDES (see Fig 2-2) <1> selects best system clock, best recovered line clock. hitless switching, frequency conversion, <N> jitter cleanup <N> Line Card (N of N) <N> <N> 2