Short Form Data Sheet April 2012 DS31415 3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock General Description Features Three Input Clocks The DS31415 is a flexible, high-performance timing IC for diverse frequency conversion and frequency Differential or CMOS/TTL Format synthesis applications. On each of its three input clocks Any Frequency from 2kHz to 750MHz and four output clocks, the device can accept or Fractional Scaling for 64B/66B and FEC Scaling generate nearly any frequency between 2kHz and (e.g., 64/66, 237/255, 238/255) or Any Other 750MHz. Downscaling Requirement Continuous Input Clock Quality Monitoring The input clocks are divided down, fractionally scaled as Three 2/4/8kHz Frame Sync Inputs needed, and continuously monitored for activity and High-Performance DPLL frequency accuracy. The best input clock is selected, manually or automatically, as the reference clock for the Hitless Reference Switching on Loss of Input rest of the device. A flexible, high-performance digital Automatic or Manual Phase Build-Out PLL locks to the selected reference and provides Holdover on Loss of All Inputs programmable bandwidth, very high resolution holdover Programmable Bandwidth, 0.5mHz to 400Hz capability, and truly hitless switching between input Two Digital Frequency Synthesizers clocks. The digital PLL is followed by a clock synthesis Produce Any 2kHz Multiple Up to 77.76MHz subsystem that has two fully programmable digital Per-DFS Phase Adjustment frequency synthesis blocks, a high-speed low-jitter High-Performance Output APLL APLL, and four output clocks, each with its own 32-bit divider and phase adjustment. The APLL provides Output Frequencies to 750MHz fractional scaling and output jitter less than 1ps RMS. High Resolution Fractional Scaling for FEC and For telecom systems, the DS31415 has all required 64B/66B (e.g., 255/237, 255/238, 66/64) or Any Other Scaling Requirement features and functions to serve as a central timing Less than 1ps RMS Output Jitter function or as a line card timing IC. Four Output Clocks in Two Groups In addition the DS31415 has an embedded IEEE 1588 clock that can be steered by system software to follow a Nearly Any Frequency from < 1Hz to 750MHz time master elsewhere in the system or elsewhere in Each Group Slaves to a DFS Clock, Any APLL the network. This clock has all necessary features to be Clock, or Any Input Clock (Divided and Scaled) the central time clock in a 1588 ordinary clock, Each Has a Differential Output (3 CML, 4 LVDS/ boundary clock or transparent clock. LVPECL) and Separate CMOS/TTL Output 32-Bit Frequency Divider Per Output Applications Two Sync Pulse Outputs: 8kHz and 2kHz Frequency Conversion and IEEE1588 Time/Frequency IEEE 1588 Clock Features -8 Applications in a Wide Variety of Equipment Types Steerable by Software with 2 ns Time -32 Resolution and 2 ns Frequency Resolution Telecom Line Cards or Timing Cards with Any Mix of 4ns Input Timestamp Accuracy and Output SONET/SDH, Synchronous Ethernet and/or OTN Edge Placement Accuracy Ports in WAN Equipment Including MSPPs, Ethernet Programmable Clock and Time-Alignment I/O to Switches, Routers, DSLAMs, and Base Stations Synchronize All 1588 Devices in Large Systems Supports 1588 OC, BC, and TC Architectures Ordering Information General Features PART TEMP RANGE PIN-PACKAGE Suitable Line Card IC or Timing Card IC for DS31415GN+ -40 C to +85 C 256 CSBGA Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU +Denotes a lead(Pb)-free/RoHS-compliant package. Accepts and Produces Nearly Any Frequency SPI is a trademark of Motorola, Inc. from 1Hz Up to 750MHz Internal Compensation for Local Oscillator Frequency Error SPI Processor Interface 1.8V Operation with 3.3V I/O (5V Tolerant) 1 Short Form Data Sheet DS31415 Application Example Typical Application Example, Traditional Frequency Synchronization clock monitoring and selection, hitless switching, holdover, phase build-out, frequency conversion, fractional scaling, jitter attenuation 19.44MHz, 38.88MHz, 19.44MHz, 38.88MHz, 25MHz, etc. 25MHz, etc. OC1 OC1POS/NEG IC1 system clocks to line cards recovered line clocks outputs from APLL: <1ps rms jitter, OC2 from system backplane, DS31415 IC2 outputs from DFS: ~40ps rms jitter OC2POS/NEG SDH, SyncE, OTN, etc. MFSYNC time alignment signal to line cards (e.g. 1 PPS) This diagram is just one example. MANY other applications are possible. Typical Application Example, Frequency and Time Synchronization Processor packet data to/from central switch function 1588 Software Local OSC TCXO or SPI OCXO DS31415 1588 system time, e.g. 1 PPS from port cards, Clock line clocks, e.g. 25MHz for SyncE or system clock, e.g. 25MHz to all port cards DPLL 1588+SyncE operation other clocks 2