MCP3910 3V Two-Channel Analog Front End Features: Description: The MCP3910 is a 3V two-channel Analog Front End Two Synchronous Sampling 24-bit Resolution (AFE), containing two synchronous sampling delta- Delta-Sigma A/D Converters sigma, Analog-to-Digital Converters (ADC), two 93.5 dB SINAD, -107 dBc Total Harmonic programmable gain amplifiers (PGA), phase delay th Distortion (THD) (up to 35 harmonic), 112 dB compensation block, low-drift internal voltage Spurious-Free Dynamic Range (SFDR) for Each reference, digital offset and gain errors calibration Channel registers, and high-speed 20MHz SPI-compatible Flexible Serial Interface that Includes Both SPI serial interface. and a Simple 2-Wire Interface Ideal for Polyphase The MCP3910 ADCs are fully configurable with Shunt Energy Meters features such as: 16-/24-bit resolution, Oversampling Enables 0.1% Typical Active Power Measurement Ration (OSR) from 32 to 4096, gain from 1x to 32x, Error over a 10,000:1 Dynamic Range independent Shutdown and Reset, dithering and auto- Advanced Security Features: zeroing. Communication is largely simplified with 8-bit - 16-bit Cyclic Redundancy Check (CRC) commands, including various continuous read/write Checksum on All Communications for Secure modes and 16-/24-/32-bit data formats that can be Data Transfers accessed by the Direct Memory Access (DMA) of an 8-/16- or 32-bit MCU, and with the separate data ready - 16-bit Cyclic Redundancy Check (CRC) pin that can directly be connected to an Interrupt Checksum and Interrupt Alert for Register- Request (IRQ) input of an MCU. Map Configuration The MCP3910 includes advanced security features to - Register-Map Lock with 8-bit Secure Key secure the communications and the configuration 2.7V 3.6V AV , DV DD DD settings, such as a CRC-16 checksum on both serial Programmable Data Rate, up to 125 ksps: data outputs and on the static register map - 4 MHz Maximum Sampling Frequency configuration. It also includes a register-map lock - 16 MHz Maximum Master Clock through an 8-bit password to stop unwanted write commands from processing. Oversampling Ratio, up to 4096 For polyphase shunt-based energy meters, the Ultra Low-Power Shutdown Mode with < 10 A MCP3910 2-Wire serial interface greatly reduces -122 dB Crosstalk between Channels system cost, requiring only a single bidirectional Low Drift 1.2V Internal Voltage Reference: isolator per phase. 9 ppm/C The MCP3910 is capable of interfacing a variety of Differential Voltage Reference Input Pins voltage and current sensors, including shunts, current High-Gain Programmable Gain Amplifier (PGA) transformers, Rogowski coils and Hall-effect sensors. on Each Channel (up to 32 V/V) Phase Delay Compensation with 1 s Time Applications: Resolution Single-Phase and Polyphase Energy Meters Separate Data Ready Pin for Easy Synchronization Energy Metering and Power Measurement Individual 24-bit Digital Offset and Gain Error Automotive Correction for Each Channel Portable Instrumentation High-Speed 20 MHz SPI Interface with Mode 0,0 Medical and Power Monitoring and 1,1 Compatibility Audio/Voice Recognition Continuous Read/Write Modes for Minimum Isolated Sensor Applications Communication with Dedicated 16-/32-bit Modes Available in 20-lead QFN and SSOP Packages Extended Temperature Range: -40C to +125C (All Specifications are Valid Down to -45C Operation) 2012-2014 Microchip Technology Inc. DS20005116B-page 1MCP3910 Package Type MCP3910 MCP3910 SSOP 4x 4 QFN* RESET/OSR0 SDI/OSR1 1 20 DV 2 19 SDO DD 3 18 SCK/MCLK AV DD CS/BOOST CH0+ 4 17 5 16 OSC2/MODE CH0- 20 19 18 16 17 CH1- OSC1/CLKI/GAIN0 6 15 CH0+ 15 SCK/MCLK 1 CH1+ 7 14 DR/GAIN1 14 A CH0- CS/BOOST 8 13 MDAT0 2 GND EP 9 12 MDAT1 13 OSC2/MODE REFIN+/OUT CH1- 3 21 REFIN- 10 11 D 12 CH1+ OSC1/CLKI/GAIN0 GND 4 11 DR/GAIN1 A 5 GND 67 8 9 10 * Includes Exposed Thermal Pad (EP) see Table 3-1. Functional Block Diagram AV DV DD DD REFIN+/OUT Voltage VREFEXT AMCLK Xtal Oscillator OSC1/CLKI/GAIN0 Reference MCLK Clock + V Generation REF DMCLK/DRCLK OSC2/MODE - REFIN- Vref- Vref+ ANALOG DIGITAL DMCLK OSR<2:0> PRE<1:0> 3 SINC + OFFCAL CH0 GAINCAL CH0 1 SINC <23:0> <23:0> CH0+ + MOD<3:0> DATA CH0 + X <23:0> CH0- - DR/GAIN1 PGA SDO Modulator Phase PHASE <11:0> Digital Shifter Interfaces RESET/OSR0 OFFCAL CH1 GAINCAL CH1 (SPI & 2-wire) SDI/OSR1 <23:0> <23:0> CH1+ + SCK DATA CH1 MOD<7:4> + X CS/BOOST <23:0> CH1- - 3 PGA SINC + 1 Modulator SINC EN MDAT DUAL ADC MDAT0 Modulator MOD<7:0> Output Block MDAT1 POR POR AV DD DV DD Monitoring Monitoring A GND DGND DS20005116B-page 2 2012-2014 Microchip Technology Inc. REFIN+/OUT AV DD REFIN- DV DD D RESET/OSR0 GND SDI/OSR1 MDAT1 MDAT0 SDO