MIC95410 6.6m R , 7A, 5.5V V Load Switch in DS(ON) IN 1.2mm 2.0mm QFN Package General Description Features The MIC95410 is a high-side load switch for computing Ultra-low R : 6.6m typical DS(on) and ultra-dense embedded computing boards where high- True 7A current capability current low-voltage rails from sub-1V to 5.5V have to be Power rail switching from sub-1V to 5.5V sectioned. The integrated 6.6m R N-channel DS(ON) Bias voltage form 2.7V to 9V MOSFET ensures low voltage drop and low power dissipation while delivering up to 7A of load current. 1A OFF-state bias supply current 1A OFF-state power switch leakage current The MIC95410 is internally powered by a separated bias Adjustable slew rate for inrush current limiting by voltage from 2.7V to 9V. It includes a TTL-logic level to external capacitor gate a voltage translator driving a charge pump, and an output discharge function when disabled. The OFF-state Load discharge current from bias supply (VS) and the power switch OFF- TTL-compatible control input state leakage current (I ) are both below 1A. OFF 10-pin 1.2mm 2.0mm QFN package, 0.5mm pin pitch The MIC95410 provides user-adjustable slew-rate- 40C to +125C junction temperature range controlled turn-on to limit the inrush current to the input supply voltage. Applications The MIC95410 is available in a thermally efficient, space- Embedded computing boards saving 10-pin 1.2mm x 2.0mm QFN package with 0.5mm Servers pin pitch and an operating junction temperature range from Data storage equipment 40C to +125C. Datasheets and support documentation are available on Micrels web site at: www.micrel.com. Typical Application MIC95410 Load Switch Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. MIC95410 Ordering Information Junction Temperature (1) (1) Part Number Marking Package Lead Finish Range MIC95410YFL 9541 40C to +125C 10-Pin 1.2mm 2.0mm QFN Pb-Free Note: 1. QFN is a GREEN, RoHS-compliant package. Lead finish is Matte Tin. Mold compound is Halogen Free. Pin Configuration 10-Pin 1.2mm 2.0mm QFN (FL) (Top View) Pin Description Pin Number Pin Name Pin Function Not internally connected. It is recommended to connect pin 1 to IN such that the width of the input 1 NC trace can be maximized in the layout. 2, 3, E1 IN Power switch input (up to 5.5V). 4 GND Driver ground and discharge return. 5 VS Bias supply input (2.7V to 9V). Bypass with 4.7F ceramic capacitor to GND. 6, 7, 8, E2 OUT Power switch output. Gate connection of power FET. Add a ceramic capacitor from GC to ground GND for slew rate 9 GC control. Control input. TTL compatible. Logic high enables the power switch. A logic low disables the power 10 CTL switch and discharges OUT. Revision 1.0 October 30, 2014 2