MT8806AE1 Microchip

MT8806 ISO-CMOS 8x4Analog Switch Array Data Sheet September 2011 Features Internal control latches and address decoder Ordering Information Short set-up and hold times MT8806APR1 28 Pin PLCC* Tape & Reel Wide operating voltage: 4.5 V to 13.2 V MT8806AP1 28 Pin PLCC* Tubes MT8806AE1 24 Pin PDIP* Tubes 12Vpp analog signal capability * Pb free Matte Tin R 65 max. V =12 V, 25 C ON DD -40 C to +85 C R 10 V =12 V, 25 C ON DD Full CMOS switch for low distortion Description Minimum feedthrough and crosstalk Separate analog and digital reference supplies The Zarlink MT8806 is fabricated in Zarlinks ISO- CMOS technology providing low power dissipation and Low power consumption ISO-CMOS technology high reliability. The device contains a 8 x 4 array of crosspoint switches along with a 5 to 32 line decoder Applications and latch circuits. Any one of the 32 switches can be addressed by selecting the appropriate five address Key systems bits. The selected switch can be turned on or off by PBX systems applying a logical one or zero to the DATA input. V is SS the ground reference of the digital inputs. The range of Mobile radio the analog signal is from V to V . Chip Select (CS) DD EE Test equipment/instrumentation allows the crosspoint array to be cascaded for matrix expansion. Analog/digital multiplexers Audio/Video switching CS STROBE DATA RESET VDD VEE VSS 11 AX0 AX1 8 x 4 5 to 32 Switch Xi I/O Latches AY0 Decoder (i=0-3) Array AY1 32 32 AY2 Yi I/O (i=0-7) Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved.MT8806 Data Sheet 1 24 Y2 VDD 2 23 Y1 Y3 22 Y0 3 Y4 NC 5 25 Y5 21 6 24 Y6 DATA 4 Y5 DATA 7 23 Y7 5 20 X0 X0 Y6 AX0 8 22 RESET 19 AX0 6 Y7 X1 9 21 STROBE 18 X1 7 RESET AX1 10 20 AY2 17 AX1 8 STROBE 11 19 X2 NC 16 X2 9 AY2 15 CS 10 AY1 X3 14 11 AY0 VSS 13 12 VEE 28 PIN PLCC 24 PIN PLASTIC DIP Figure 2 - Pin Connections Change Summary Changes from the May 2005 issue to the September 2011 issue. Page Item Change 1 Ordering Information Removed leaded packages as per PCN notice. Pin Description Pin Name Description PDIP PLCC 1-3 1-3 Y2-Y0 Y2-Y0 Analog (Inputs/Outputs): these are connected to the Y2-Y0 columns of the switch array. 46 DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. 57 X0 X0 Analog (Input/Output): this is connected to the X0 row of the switch array. 6 8 AX0 X0 Address Line (Input) 79 X1 X1 Analog (Input/Output): this is connected to the X1 row of the switch array. 8 10 AX1 X1 Address Line (Input) 911 X2 X2 Analog (Input/Output): this is connected to the X2 row of the switch array. 10 12 CS Chip Select (Input): this is used to select the device. Active High. 11 13 X3 X3 Analog (Input/Output): this is connected to the X3 row of the switch array. 12 14 V Digital Ground Reference SS 2 Zarlink Semiconductor Inc. 12 4 13 3 14 2 15 1 16 28 17 27 18 26 NC Y0 Y1 Y2 VDD Y3 Y4 AY1 CS X3 VSS VEE AY0 NC