MT9074 T1/E1/J1 Single Chip Transceiver Data Sheet August 2011 Features Combined E1 (PCM30) and T1 (D4/ESF) framer, Ordering Information Line Interface Unit (LIU) and link controller with optional digital framer only mode MT9074AL1 100 Pin MQFP* Trays MT9074AP1 68 Pin PLCC* Tubes In T1 mode the LIU can recover signals MT9074APR1 68 Pin PLCC* Tape & Reel attenuated by up to 30 dB (5000 ft. of 24 AWG *Pb Free Matte Tin cable) -40 C to +85 C In E1 mode the LIU can recover signals attenuated by up to 30 dB (1900 m. of 0.65 mm cable) Hardware data link access Two HDLCs: FDL and channel 24 in T1 mode, JTAG Boundary Scan timeslot 0 (Sa bits) and timeslot 16 in E1 mode Applications Two-frame elastic buffer in Rx & Tx (T1) directions E1/T1 add/drop multiplexers and channel banks Programmable transmit delay through transmit CO and PBX equipment interfaces slip buffer Primary Rate ISDN nodes Low jitter DPLL for clock generation Digital Cross-connect Systems (DCS) Enhanced alarms, performance monitoring and error insertion functions * MT9074A was revised after its market introduction. Software can confirm that the installed chip is the most recent revision of MT9074A Intel or Motorola non-multiplexed parallel as follows: microprocessor interface 1. In T1 mode, the LSB (Least Significant Bit) of the ST-BUS 2.048 Mbit/s backplane bus for both data Synchronization Status Word - bit 0, Page 3 Address 10H is set high. and signaling 2. Batch codes 61755.0 or higher, and/or date code beginning with Japan Telecom J1 Framing and Yellow Alarm 00, 01, 02, etc. TxDL TxDLCLK TxMF TxAO TxB TxA DSTi ST-BUS Transmit Framing, Error, Line TTIP CSTi Interface Test Signal Generation and Slip Buffer Driver TRING Tdi Tdo PL Loop Tms ST Loop Tclk National Trst Bit Buffer S/FR Jitter Attenuator IRQ BS/LS & Clock Control OSC1 D7~D0 Data Link, OSC2 CAS AC4 HDLC0 Buffer AC0 DG Loop HDLC1 R/W/WR CS RTIP DS/RD RRING DSTo Receive Framing, Performance Monitoring, ST-BUS CSTo Interface Alarm Detection, 2 Frame Slip Buffer RxDLCLK RxDL RxMF LOS RxFP E1.5o F0b C4b Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002-2011, Zarlink Semiconductor Inc. All Rights Reserved. Microprocessor IEEE 1149.1 Interface Clock,Data Pulse Recovery Generator RM Loop Rx Equalizer & Data Slicer MT LoopMT9074 Data Sheet Description The MT9074 is a single chip device, operable in either T1 or E1 mode, integrating either an advanced T1 (T1 mode) or PCM30 (E1 mode) framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane providing selectable data link access with optional HDLC controllers for either the FDL bits and channel 24 (T1 mode) or S bits and channel 16 (E1 mode). The LIU a interfaces the framer to T1 (T1 mode) or PCM30 (E1 mode) transformer-isolated four-wire line with minimal external components required. In T1 mode, the MT9074 supports D4, ESF and SLC-96 formats, meeting the latest recommendations including ITU I.431, AT&T PUB43801, TR-62411, ANSI T1.102, T1.403 and T1.408. In E1 mode the MT9074 supports the latest ITU-T Recommendations including G.703, G.704, G.706, G.732, G.775, G.796, G.823 for PCM30, and I.431 for ISDN primary rate. It also supports ETSI ETS 300 011, ETS 300 166 and ETS 300 233. Change Summary Changes from the August 2005 issue to the August 2011 issue. Page Item Change 1 Ordering Information Removed leaded packages as per PCN notice. 2 Zarlink Semiconductor Inc.