8 Mbit Firmware Hub SST49LF008A SST49LF008A8 Mb Firmware Hub for Intel 8xx Chipsets Data Sheet FEATURES: Firmware Hub for Intel 8xx Chipsets Two Operational Modes 8 Mbit SuperFlash memory array for code/data Firmware Hub Interface (FWH) Mode for storage In-System operation Parallel Programming (PP) Mode for fast 1024K x8 production programming Flexible Erase Capability Firmware Hub Hardware Interface Mode Uniform 4 KByte Sectors 5-signal communication interface supporting Uniform 64 KByte overlay blocks byte Read and Write 64 KByte Top Boot Block protection 33 MHz clock frequency operation Chip-Erase for PP Mode Only WP and TBL pins provide hardware write Single 3.0-3.6V Read and Write Operations protect for entire chip and/or top Boot Block Superior Reliability Block Locking Register for all blocks Standard SDP Command Set Endurance:100,000 Cycles (typical) Data Polling and Toggle Bit for End-of-Write Greater than 100 years Data Retention detection Low Power Consumption 5 GPI pins for system design flexibility Active Read Current: 6 mA (typical) 4 ID pins for multi-chip selection Standby Current: 10 A (typical) Parallel Programming (PP) Mode Fast Sector-Erase/Byte-Program Operation 11-pin multiplexed address and Sector-Erase Time: 18 ms (typical) 8-pin data I/O interface Block-Erase Time: 18 ms (typical) Supports fast In-System or PROM programming Chip-Erase Time: 70 ms (typical) for manufacturing Byte-Program Time: 14 s (typical) CMOS and PCI I/O Compatibility Chip Rewrite Time: 15 seconds (typical) Packages Available Single-pulse Program or Erase Internal timing generation 32-lead PLCC 32-lead TSOP (8mm x 14mm) 40-lead TSOP (10mm x 20mm) Non-Pb (lead-free) packages available All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST49LF008A flash memory devices are designed to The SST49LF008A devices write (Program or Erase) with be read-compatible with the Intel 82802 Firmware Hub a single 3.0-3.6V power supply. They use less energy dur- (FWH) device for PC-BIOS application. These devices pro- ing Erase and Program than alternative flash memory tech- vide protection for the storage and update of code and data nologies. The total energy consumed is a function of the in addition to adding system design flexibility through five applied voltage, current and time of application. Since for general purpose inputs. Two interface modes are sup- any given voltage range, the SuperFlash technology uses ported by the SST49LF008A: Firmware Hub (FWH) Inter- less current to program and has a shorter Erase time, the face mode for in-system programming and Parallel total energy consumed during any Erase or Program oper- Programming (PP) mode for fast factory programming of ation is less than alternative flash memory technologies. PC-BIOS applications. The SST49LF008A products provide a maximum Byte- Program time of 20 sec. The entire memory can be The SST49LF008A flash memory devices are manufac- erased and programmed byte-by-byte typically in 15 sec- tured with SSTs proprietary, high performance SuperFlash onds when using status detection features such as Toggle technology. The split-gate cell design and thick-oxide tun- Bit or Data Polling to indicate the completion of Program neling injector attain better reliability and manufacturability operation. The SuperFlash technology provides fixed Erase compared with alternate approaches. The SST49LF008A and Program times independent of the number of Erase/ devices significantly improve performance and reliability, Program cycles performed. Therefore the system software while lowering power consumption. 2006 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. S71161-11-000 3/06 Intel is a registered trademark of Intel Corporation. 1 These specifications are subject to change without notice.8 Mbit Firmware Hub SST49LF008A Data Sheet or hardware does not have to be calibrated or correlated to To meet high density, surface mount requirements, the the cumulated number of Erase/Program cycles as is nec- SST49LF008A devices are offered in a 32-lead TSOP essary with alternative flash memory technologies, whose package. In addition, the SST49LF008A is offered in 32- Erase and Program time increase with accumulated Erase/ lead PLCC and 40-lead TSOP packages. See Figures 2, 3, Program cycles. and 4 for pin assignments and Table 1 for pin descriptions. To protect against inadvertent write, the SST49LF008A devices employ hardware and software data (SDP) protec- tion schemes. It is offered with typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. TABLE OF CONTENTS PRODUCT DESCRIPTION . 1 LIST OF FIGURES . 4 LIST OF TABLES . 5 FUNCTIONAL BLOCK DIAGRAM 6 PIN ASSIGNMENTS 7 DEVICE MEMORY MAP 10 DESIGN CONSIDERATIONS 11 PRODUCT IDENTIFICATION 11 MODE SELECTION 11 FIRMWARE HUB (FWH) MODE 11 Device Operation . 11 Firmware Hub Interface Cycles . 11 Abort Mechanism . 14 Response To Invalid Fields 14 Device Memory Hardware Write Protection . 14 Reset . 14 Write Operation Status Detection . 14 Data Polling (DQ ) . 15 7 Toggle Bit (DQ ) 15 6 Multiple Device Selection . 15 REGISTERS . 15 General Purpose Inputs Register . 15 Block Locking Registers 15 Write Lock . 17 Lock Down 17 JEDEC ID Registers . 17 2006 Silicon Storage Technology, Inc. S71161-11-000 3/06 2