Obsolete Device Please contact Microchip Sales for replacement information. 16 Mbit LPC Serial Flash SST49LF016C EOL Data Sheet The SST49LF016C flash memory device is designed to interface with host con- trollers (chipsets) that support a low pin-count (LPC) interface for system firmware applications. Complying with LPC Interface Specification 1.1, SST49LF016C sup- ports a Burst-Read data transfer of 15.6 MBytes per second at 33 MHz clock speed and 31.2 MBytes per second at 66 MHz clock speed, up to 128 bytes in a single operation Features Operational Clock Frequency Security ID Feature 33 MHz 256-bit Secure ID space 66 MHz - 64-bit Unique Factory Pre-programmed Device Identi- fier Organized as 2M x8 - 192-bit User-Programmable OTP Superior Reliability Conforms to LPC Interface Specification v1.1 Endurance: 100,000 Cycles (typical) Support Multi-Byte Firmware Memory Read/Write Greater than 100 years Data Retention Cycles Low Power Consumption Single 3.0-3.6V Read and Write Operations Active Read Current: 12 mA (typical) LPC Mode Standby Current: 10 A (typical) 5-signal LPC bus interface for both in-system and fac- Uniform 4 KByte sectors tory programming using programmer equipment Multi-Byte Read data transfer rate 35 Overlay Blocks: one 16-KByte Boot Block, two 8- 15.6 MB/s 33 MHz PCI clock and KByte Parameter Blocks, one 32-Kbyte Parameter 31.2 MB/s 66 MHz clock Block, thirty-one 64-KByte Main Blocks. - Firmware Memory Read cycle supporting 1, 2, 4, 16, and 128 Byte Read Fast Sector-Erase/Program Operation - Firmware Memory Write cycle supporting Sector-Erase Time: 18 ms (typical) 1, 2, and 4 Byte Write Block-Erase Time: 18 ms (typical) 33 MHz/66 MHz clock frequency operation Program Time: 7 s (typical) WP /AAI and TBL pins provide hardware Write protect for entire chip and/or top Boot Block Auto Address Increment (AAI) for Rapid Factory Block Locking Registers for individual block Read-Lock, Programming (High Voltage Enabled) Write-Lock, and Lock-Down protection 5 GPI pins for system design flexibility RY/BY pin for End-of-Write detection 4 ID pins for multi-chip selection Multi-Byte Program Multi-Byte capability registers Chip Rewrite Time: 4 seconds (typical) (read-only registers) Status register for End-of-Write detection Packages Available Program-/Erase-Suspend 32-lead PLCC Read or Write to other blocks during 32-lead TSOP (8mm x 14mm) Program-/Erase-Suspend 40-lead TSOP (10mm x 20mm) All devices are RoHS compliant Two-cycle Command Set 2016 www.microchip.com DS20005029B 02/1616 Mbit LPC Serial Flash SST49LF016C EOL Data Sheet Product Description The SST49LF016C flash memory device is designed to interface with host controllers (chipsets) that support a low-pin-count (LPC) interface for system firmware applications. Complying with LPC Inter- face Specification 1.1, SST49LF016C supports a Burst-Read data transfer of 15.6 MBytes per second at 33 MHz clock speed and 31.2 MBytes per second at 66 MHz clock speed, up to 128 bytes in a sin- gle operation. The LPC interface operates with 5 signal pins versus 28 pins of a 8-bit parallel flash memory. This frees up pins on the ASIC host controller resulting in lower ASIC costs and a reduction in overall sys- tem costs due to simplified signal routing. This 5-signal LPC interface supports both in-system and rapid factory programming using programmer equipment. A high voltage pin (WP /AAI) enables Auto Address Increment (AAI) mode. Via the software registers, the SST49LF016C offers hardware block protection and individual block protection for critical system code and data. The 256-bit Security ID space is comprised of a 64-bit fac- tory pre-programmed unique number and a 192-bit One-Time-Programmable (OTP) area. This Secu- rity ID permits the use of new security techniques and implementation of a new data protection scheme. To protect against inadvertent write, the SST49LF016C device has on-chip hardware and software write protection schemes. The SST49LF016C also provides general purpose inputs (GPI) for system design flexibility. Manufactured with SST proprietary, high-performance SuperFlash technology, SST49LF016C has a split-gate cell design and thick-oxide tunneling injector for greater reliability and manufacturability com- pared with alternative technology approaches. The SST49LF016C significantly improves performance and reliability, while lowering power consump- tion. The total energy consumed is a function of the applied voltage, current and time of application. Because the SST49LF016C writes in-system with a single 3.0-3.6V power supply, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SuperFlash technology provides fixed Erase and Program time, independent of the number of Erase/Program cycles performed. This feature eliminates system software or hardware calibration or erase cycle correlation which is necessary with alternative flash memory technologies, whose Erase and Program time increase with accumulated Erase/Program cycles. The SST49LF016C product provides a maximum program time of 10 s per byte with a single-byte Program operation effectively 5 s per byte with a dual-byte Program operation and 2.5 s per byte with a quad-byte Program operation. The SST49LF016C is offered in 32-PLCC, 32-TSOP, and 40-TSOP packages. See Figures 3, 4, and 5 for pin assignments and Table 1 for pin descriptions. 2016 DS20005029B 02/16 2