Precision Edge 3.3V, 3.2Gbps DIFFERENTIAL 4:1 LVDS SY89547L Micrel, Inc. Precision Edge MULTIPLEXER with 1:2 FANOUT and SY89547L INTERNAL TERMINATION FEATURES Selects among four differential inputs Precision Edge Provides two copies of the selected input Guaranteed AC performance over temp and voltage: DESCRIPTION DC-to > 3.2Gbps data rate throughput < 620ps In-to-Out t pd The SY89547L is a precision, high-speed 4:1 differential < 150ps t /t r f multiplexer that provides two copies of the selected input. Unique input isolation design minimizes crosstalk The high speed LVDS (350mV) compatible outputs with a guaranteed throughput of up to 3.2Gbps over temperature Ultra-low jitter design: and voltage. < 1ps random jitter RMS < 10ps deterministic jitter The SY89547L differential inputs include Micrels unique, PP < 10ps total jitter (clock) 3-pin internal termination design that allows access to the PP < 0.7ps crosstalk-induced jitter termination network through a V pin. This feature allows RMS T the device to easily interface to different logic standards, Internal input termination both AC- and DC-coupled without external resistor-bias and Unique input termination and V pin accepts DC- T termination networks. The result is a clean, stub-free, low coupled and AC-coupled inputs (LVDS, LVPECL, jitter interface solution. CML) The SY89547L operates from a single 3.3V supply, and 350mV LVDS output swing is guaranteed over the full industrial temperature range Power supply 3.3V 10% (40C to +85C). For applications that require a 2.5V supply, 40C to +85C temperature range consider the SY89546U. For applications that only require one differential output, consider the SY89544U or SY89545L. Available in 32-pin (5mm x 5mm) MLF package The SY89547L is part of a Micrels Precision Edge product family. All support documentation can be found on Micrels APPLICATIONS web site at: www.micrel.com. SONET/SDH multi-channel select applications FUNCTIONAL BLOCK DIAGRAM Fibre Channel applications IN0 50 GigE applications V T0 50 4:1 MUX /IN0 1:2 Fanout 0 TYPICAL PERFORMANCE IN1 50 V T1 Q0 50 Output Amplitude /Q0 /IN1 1 vs. Frequency 400 LVDS MUX 350 IN2 2 300 Q1 50 250 /Q1 V T2 200 50 S1 /IN2 150 S0 3 100 50 IN3 0 50 0 1000 2000 3000 4000 5000 6000 V FREQUENCY (MHz) T3 50 /IN3 SEL0 (CMOS/TTL) Precision Edge is a registered trademark of Micrel, Inc. SEL1 (CMOS/TTL) MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. Rev.: D Amendment: /0 M9999-091809 1 Issue Date: September 2009 hbwhelp micrel.com or (408) 955-1690 OUTPUT AMPLITUDE (mV) Precision Edge Micrel, Inc. SY89547L PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead 32 31 30 29 28 27 26 25 Part Number Type Range Marking Finish 1 24 VCC VCC 23 /IN0 2 IN3 SY89547LMI MLF-32 Industrial SY89547L Sn-Pb VT0 3 22 VT3 (2) SY89547LMITR MLF-32 Industrial SY89547L Sn-Pb IN0 4 21 /IN3 5 20 (3) VCC VCC SY89547LMG MLF-32 Industrial SY89547L with Pb-Free 6 19 SEL0 SEL1 Pb-Free bar-line indicator NiPdAu 7 18 GND GND (2, 3) VCC 8 17 VCC SY89547LMGTR MLF-32 Industrial SY89547L with Pb-Free 910 111213141516 Pb-Free bar-line indicator NiPdAu Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. 32-Pin MLF 3. Recommended for new designs. PIN DESCRIPTION Pin Number Pin Name Pin Function 4, 2, 32, IN0, /IN0, Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs 30, 27, 25, 23, 21 IN1, /IN1, accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally IN2, /IN2, terminates to a V pin through 50 . Note that these inputs will default to an indeterminate T IN3, /IN3 state if left open. Unused differential input pairs can be terminated by connecting one input to V and the complementary input to GND through a 1k resistor. The V pin is to be CC T left open in this configuration. Please refer to the Input Interface Applications section for more details. 3, 31, 26, 22 VT0, VT1, Input Termination Center-Tap: Each side of the differential input pair, terminates to a V T VT2, VT3 pin. The V , V , V , V pins provide a center-tap to a termination network for TA0 TA1 TB0 TB1 maximum interface flexibility. See Input Interface Applications section for more details. 6, 19 SEL0, SEL1 These single-ended TTL/CMOS-compatible inputs select the inputs to the multiplexers. Note that these inputs are internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. Input switching threshold is V /2. CC 1, 5, 8, VCC Positive Power Supply: Bypass with 0.1 F 0.01 F low ESR capacitors. 17, 20, 24, 28, 29 10, 11, 14, 15 Q0, /Q0, Differential Outputs: These LVDS output pairs are the outputs of the device. They are a Q1, /Q1 logic function of the INA0, INA1, INB0, INB1 and SELA and SELB inputs. Please refer to the Truth Table for details. If an output is not used, it must be terminated with 100 across the differential pair. 7, 9, 12, 13, 16, 18 GND, Ground: Ground pin and exposed pad must be connected to the same ground plane. Exposed pad M9999-091809 2 hbwhelp micrel.com or (408) 955-1690 IN1 GND Q0 VT1 /Q0 /IN1 GND VCC GND VCC Q1 IN2 /Q1 VT2 GND /IN2