M58BW016FB7T3F Micron

M58BW016DB M58BW016DT M58BW016FT M58BW016FB 16 Mbit (512 Kbit x 32, boot block, burst) 3 V supply Flash memories Features Supply voltage V = 2.7 V to 3.6 V for program, erase DD and read V = V = 2.4 V to 3.6 V for I/O DDQ DDQIN buffers V = 12 V for fast program (optional) PP High performance Access times: 70, 80 ns PQFP80 (T) 56 MHz effective zero wait-state burst read Synchronous burst read Asynchronous page read Hardware block protection LBGA WP pin for write protect of the 2 outermost parameter blocks and all main blocks RP pin for write protect of all blocks Optimized for FDI drivers LBGA80 10 12 mm Fast program / erase suspend latency time < 6 s Common Flash interface Memory blocks RoHS packages available 8 parameters blocks (top or bottom) 31 main blocks Low power consumption 5 A typical deep power-down 60 A typical standby for M58BW016DT/B 150 A typical standby for M58BW016FT/B Automatic standby after asynchronous read Electronic signature Manufacturer code: 20h Top device code: 8836h Bottom device code: 8835h 100 K write/erase cycling + 20 years data retention (minimum) High reliability level with over 1 M write/erase cycling sustained July 2011 Rev 18 1/70 www.numonyx.com 1Contents M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Contents 1 Description . 7 1.1 Block protection .11 2 Signal descriptions . 14 2.1 Address inputs (A0-A18) . 14 2.2 Data inputs/outputs (DQ0-DQ31) . 14 2.3 Chip Enable (E) 14 2.4 Output Enable (G) 14 2.5 Output Disable (GD) . 15 2.6 Write Enable (W) . 15 2.7 Reset/Power-down (RP) 15 2.8 Latch Enable (L) 15 2.9 Burst Clock (K) . 16 2.10 Burst Address Advance (B) . 16 2.11 Valid Data Ready (R) 16 2.12 Write Protect (WP) 16 2.13 Supply voltage (V DD) 16 2.14 Output supply voltage (V ) . 17 DDQ 2.15 Input supply voltage (V ) . 17 DDQIN ) 17 2.16 Program/erase supply voltage (V PP 2.17 Ground (V and V ) 17 SS SSQ 2.18 Dont use (DU) . 17 2.19 Not connected (NC) . 17 3 Bus operations 18 3.1 Asynchronous bus operations . 18 3.1.1 Asynchronous bus read . 18 3.1.2 Asynchronous latch controlled bus read 18 3.1.3 Asynchronous page read 19 3.1.4 Asynchronous bus write . 19 3.1.5 Asynchronous latch controlled bus write 19 3.1.6 Output Disable 19 2/70